SLVSCF3A June   2014  – March 2015

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Characteristics
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parametric Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Enable and Adjusting Undervoltage Lockout
      2. 9.3.2 Overvoltage Protection (OVP)
      3. 9.3.3 Hot Plug-in and In-Rush Current Control
      4. 9.3.4 Overload and Short Circuit Protection :
        1. 9.3.4.1 Overload Protection
        2. 9.3.4.2 Short Circuit Protection
        3. 9.3.4.3 Start-Up with Short on Output
        4. 9.3.4.4 Constant Current Limit Behavior During Overcurrent Faults
      5. 9.3.5 FAULT Response
      6. 9.3.6 Current Monitoring:
      7. 9.3.7 Power Good Comparator
      8. 9.3.8 IN, OUT and GND Pins
      9. 9.3.9 Thermal Shutdown:
    4. 9.4 Device Functional Modes
      1. 9.4.1 DevSleep Mode for SATA® Interface Devices
      2. 9.4.2 Shutdown Control
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 eFuse for Enterprise SSDs
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Step by Step Design Procedure
          2. 10.2.1.2.2 Programming the Current-Limit Threshold: R(ILIM) Selection
          3. 10.2.1.2.3 Undervoltage Lockout and Overvoltage Set Point
          4. 10.2.1.2.4 Programming Current Monitoring Resistor - RIMON
          5. 10.2.1.2.5 Setting Output Voltage Ramp time (tdVdT)
            1. 10.2.1.2.5.1 Case1: Start-up Without Load: Only Output Capacitance C(OUT) Draws Current During Start-up
            2. 10.2.1.2.5.2 Case 2: Start-up With Load: Output Capacitance C(OUT) and Load Draws Current During Start-up
          6. 10.2.1.2.6 Programing the Power Good Set Point
          7. 10.2.1.2.7 Support Component Selections - R6, R7 and CIN
        3. 10.2.1.3 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 Power Failure Protection and Data Retention in SSDs
      2. 10.3.2 Boost Power Rail Configuration for Data Retention in Enterprise SSDs
  11. 11Power Supply Recommendations
    1. 11.1 Transient Protection
    2. 11.2 Output Short-Circuit Measurements
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RVC|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

12 Layout

12.1 Layout Guidelines

  • For all applications, a 0.1-uF or greater ceramic decoupling capacitor is recommended between IN terminal and GND. For hot-plug applications, where input power path inductance is negligible, this capacitor can be eliminated/minimized.
  • The optimum placement of decoupling capacitor is closest to the IN and GND terminals of the device. Care must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the GND terminal of the IC. See Figure 80 for a PCB layout example.
  • High current carrying power path connections should be as short as possible and should be sized to carry at least twice the full-load current.
  • Low current signal ground (SGND), which is the reference ground for the device should be a copper plane or island.
  • Locate all TPS25940 support components: R(ILIM), CdVdT, R(IMON), and resistors for UVLO and OVP, close to their connection pin. Connect the other end of the component to the SGND with shortest trace length.
  • The trace routing for the RILIM and R(IMON) components to the device should be as short as possible to reduce parasitic effects on the current limit and current monitoring accuracy. These traces should not have any coupling to switching signals on the board.
  • The SGND plane must be connected to high current ground (main power ground) at a single point, that is at the negative terminal of input capacitor
  • Protection devices such as TVS, snubbers, capacitors, or diodes should be placed physically close to the device they are intended to protect, and routed with short traces to reduce inductance. For example, a protection Schottky diode is recommended to address negative transients due to switching of inductive loads, and it should be physically close to the OUT pins.
  • Thermal Considerations: When properly mounted the PowerPAD™ package provides significantly greater cooling ability than an ordinary package. To operate at rated power, the PowerPAD must be soldered directly to the board GND plane directly under the device. The PowerPAD is at GND potential and can be connected using multiple vias to inner layer GND. Other planes, such as the bottom side of the circuit board can be used to increase heat sinking in higher current applications. Refer to Technical Briefs: PowerPad™ Thermally Enhanced Package (TI literature Number SLMA002) and PowerPAD™ Made Easy (TI Literature Number SLMA004) or more information on using this PowerPAD™ package
  • The thermal via land pattern specific to TPS25940 can be downloaded from device webpage
  • Obtaining acceptable performance with alternate layout schemes is possible; however this layout has been shown to produce good results and is intended as a guideline.

12.2 Layout Example

TPS25940A TPS25940L Layout_slvscf3.gif
A. Optional: Needed only to suppress the transients caused by inductive load switching
Figure 80. Board Layout