SLVSCE9D June   2014  – October  2017 TPS25942A , TPS25942L , TPS25944A , TPS25944L

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Enable and Adjusting Undervoltage Lockout
      2. 9.3.2  Overvoltage Protection (OVP)
      3. 9.3.3  Hot Plug-In and In-Rush Current Control
      4. 9.3.4  Overload and Short Circuit Protection
        1. 9.3.4.1 Overload Protection
        2. 9.3.4.2 Short Circuit Protection
        3. 9.3.4.3 Start-Up With Short on Output
        4. 9.3.4.4 Constant Current Limit Behavior During Overcurrent Faults
      5. 9.3.5  Reverse Current Protection
      6. 9.3.6  FAULT Response
      7. 9.3.7  Current Monitoring
      8. 9.3.8  Power Good Comparator
      9. 9.3.9  IN, OUT and GND Pins
      10. 9.3.10 Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Diode Mode
      2. 9.4.2 Shutdown Control
      3. 9.4.3 Operational Differences Between the TPS25942 and TPS25944
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Step by Step Design Procedure
        2. 10.2.2.2 Programming the Current-Limit Threshold: R(ILIM) Selection
        3. 10.2.2.3 Undervoltage Lockout and Overvoltage Set Point
        4. 10.2.2.4 Programming Current Monitoring Resistor—RIMON
        5. 10.2.2.5 Setting Output Voltage Ramp Time (tdVdT)
          1. 10.2.2.5.1 Case1: Start-Up Without Load: Only Output Capacitance C(OUT) Draws Current During Start-Up
          2. 10.2.2.5.2 Case 2: Start-Up With Load: Output Capacitance C(OUT) and Load Draws Current During Start-Up
        6. 10.2.2.6 Programing the Power Good Set Point
        7. 10.2.2.7 Support Component Selections—R6, R7 and CIN
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 Active ORing (Auto-Power Multiplexer) Operation
        1. 10.3.1.1 N+1 Power Supply Operation
        2. 10.3.1.2 Priority Power MUX Operation
        3. 10.3.1.3 Priority MUXing With Almost Equal Rails (VIN1 ~ VIN2)
        4. 10.3.1.4 Reverse Polarity Protection
  11. 11Power Supply Recommendations
    1. 11.1 Transient Protection
    2. 11.2 Output Short-Circuit Measurements
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Related Links
    4. 13.4 Receiving Notification of Documentation Updates
    5. 13.5 Community Resources
    6. 13.6 Trademarks
    7. 13.7 Electrostatic Discharge Caution
    8. 13.8 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

Conditions are –40°C ≤ TJ = TA ≤ +125°C, 2.7 V ≤ V(IN) ≤ 18 V, V(EN/UVLO) = 2 V, V(OVP) = V(DMODE) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ, C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. Positive current into terminals. All voltages referenced to GND (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
SUPPLY VOLTAGE AND INTERNAL UNDERVOLTAGE LOCKOUT
V(IN) Operating input voltage 2.7 18 V
V(UVR) Internal UVLO threshold, rising 2.2 2.3 2.4 V
V(UVRhys) Internal UVLO hysteresis 105 116 125 mV
IQ(ON) Supply current, enabled V(EN/UVLO) = 2 V, V(IN) = 3 V 140 210 300 µA
V(EN/UVLO) = 2 V, V(IN) = 12 V 140 199 260
V(EN/UVLO) = 2 V, V(IN) = 18 V 140 202 270
IQ(OFF) Supply current, disabled V(EN/UVLO) = 0 V, V(IN) = 3 V 4 8.6 15 µA
V(EN/UVLO) = 0 V, V(IN) = 12 V 6 15 20
V(EN/UVLO) = 0 V, V(IN) = 18 V 8 18.5 25
ENABLE AND UNDERVOLTAGE LOCKOUT (EN/UVLO) INPUT
V(ENR) EN/UVLO threshold voltage, rising 0.97 0.99 1.01 V
V(ENF) EN/UVLO threshold voltage, falling 0.9 0.92 0.94 V
V(SHUTF) EN threshold voltage for Low IQ shutdown, falling 0.3 0.47 0.63 V
V(SHUTFhys) EN hysteresis for low IQ shutdown, hysteresis(1) 66 mV
IEN EN input leakage current 0 V ≤ V(EN/UVLO) ≤ 18 V –100 0 100 nA
OVER VOLTAGE PROTECTION (OVP) INPUT
V(OVPR) Overvoltage threshold voltage, rising 0.97 0.99 1.01 V
V(OVPF) Overvoltage threshold voltage, falling 0.9 0.92 0.94 V
I(OVP) OVP input leakage current 0 V ≤ V(OVP) ≤ 5 V –100 0 100 nA
DIODE MODE INPUT (DMODE)—ACTIVE HIGH
V(DMODE) DMODE threshold voltage, rising 1.6 1.85 2 V
DMODE threshold voltage, falling 0.8 0.96 1.1 V
I(DMODE) DMODE input leakage current 0.2 V ≤ V(DMODE) ≤ 18 V 0.6 1 1.25 µA
OUTPUT RAMP CONTROL (dVdT)
I(dVdT) dVdT charging current V(dVdT) = 0 V 0.85 1 1.15 µA
R(dVdT) dVdT discharging resistance EN/UVLO = 0 V, I(dVdT) = 10 mA sinking 16 24 Ω
V(dVdTmax) dVdT maximum capacitor voltage 2.6 2.88 3.1 V
GAIN(dVdT) dVdT to OUT gain ΔV(OUT)/ΔV(dVdT) 11.65 11.9 12.05 V/V
CURRENT LIMIT PROGRAMMING (ILIM)
V(ILIM) ILIM bias voltage 0.87 V
I(LIM) Current limit
I(LIM) for TPS25942(2)
I(FAULT) forTPS25944 (2)(3)		 R(ILIM) = 150 kΩ, (V(IN) – V(OUT))  = 1 V 0.53 0.58 0.63 A
R(ILIM) = 88.7 kΩ, (V(IN) – V(OUT))  = 1 V 0.9 0.99 1.07
R(ILIM) = 42.2 kΩ, (V(IN) – V(OUT)) = 1 V 1.92 2.08 2.25
R(ILIM) = 24.9 kΩ, (V(IN) – V(OUT)) = 1 V 3.25 3.53 3.81
R(ILIM) = 20 kΩ, (V(IN) – V(OUT))  = 1 V 4.09 4.45 4.81
R(ILIM) = 16.9 kΩ, (V(IN) – V(OUT))  = 1 V 4.78 5.2 5.62
R(ILIM) = OPEN, open resistor current limit (single point failure test: UL60950) 0.35 0.45 0.55
R(ILIM) = SHORT, shorted resistor current limit (single point failure test: UL60950) 0.55 0.67 0.8
DMODE = High; Non-ideal diode mode(1) 0.5 × I(LIM)
I(OS) Short-circuit current limit R(ILIM) = 42.2 kΩ, V(VIN) = 12 V, (V(IN) – V(OUT)) = 5 V 1.91 2.07 2.24 A
R(ILIM) = 24.9 kΩ, V(VIN) = 12 V, (V(IN) – V(OUT)) = 5 V 3.21 3.49 3.77
R(ILIM) = 16.9 kΩ, V(VIN) = 12 V, (V(IN) – V(OUT)) = 5 V,
–40°C ≤ TJ ≤ +85°C 		4.7 5.11 5.52
I(FASTRIP) Fast-trip comparator threshold(1)(2) 1.5 × I(LIM) + 0.375 A
CURRENT MONITOR OUTPUT (IMON)
GAIN(IMON) Gain factor I(IMON):I(OUT) 1 A ≤ I(OUT) ≤ 5 A 47.78 52.3 57.23 µA/A
MOSFET—POWER SWITCH
RON IN to OUT - ON resistance 1 A ≤ I(OUT) ≤ 5 A, TJ = 25°C 34 42 49 mΩ
1 A ≤ I(OUT) ≤ 5 A, –40°C ≤ TJ ≤ +85°C 26 42 58
1 A ≤ I(OUT) ≤ 5 A, –40°C ≤ TJ ≤ +125°C 26 42 64
PASS FET OUTPUT (OUT)
Ilkg(OUT) OUT leakage current in off state V(IN) = 18 V, V(EN/UVLO) = 0 V, V(OUT) = 0 V (sourcing) –2 0 2 µA
V(IN) = 2.7 V, V(EN/UVLO) = 0 V, V(OUT) = 18 V (sinking) 6 13 20
V(REVTH) V(IN) – V(OUT) threshold for reverse protection comparator, falling –15 –9.3 –3 mV
V(FWDTH) V(IN) – V(OUT) threshold for reverse protection comparator, rising 86 100 114 mV
FAULT FLAG (FLT)—ACTIVE LOW
R(FLT) FLT internal pull-down resistance V(OVP) = 2 V, I(FLT) = 5 mA sinking 10 18 30 Ω
I(FLT) FLT input leakage current 0 V ≤ V(FLT) ≤ 18 V –1 0 1 µA
POSITIVE INPUT for POWER-GOOD COMPARATOR (PGTH)
V(PGTHR) PGTH threshold voltage, rising 0.97 0.99 1.01 V
V(PGTHF) PGTH threshold voltage, falling 0.9 0.92 0.94 V
I(PGTH) PGTH input leakage current 0 V ≤ V(PGTH) ≤ 18 V –100 0 100 nA
POWER-GOOD COMPARATOR OUTPUT (PGOOD): ACTIVE HIGH
R(PGOOD) PGOOD internal pull-down resistance V(PGTH) = 0V, I(PGOOD) = 5 mA sinking 10 20 35 Ω
I(PGOOD) PGOOD input leakage current 0 V ≤ V(PGOOD) ≤ 18 V –1 0 1 µA
THERMAL SHUT DOWN (TSD)
T(TSD) TSD threshold(1) 160 °C
T(TSDhys) TSD hysteresis(1) 12 °C
Thermal fault: (latched or auto-retry) TPS25942L, TPS25944L Latched
TPS25942A, TPS25944A Auto-retry
(1) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's product warranty.
(2) Pulse-testing techniques maintain junction temperature close to ambient temperature. Thermal effects must be taken into account separately.
(3) The TPS25942 limits current to the programmed I(LIM) level. TPS25944 does not limit current but runs the fault timer when I(LOAD) > I(LIM).