SLVSCE9D June 2014 – October 2017 TPS25942A , TPS25942L , TPS25944A , TPS25944L
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
The device has multiple pins for input (IN) and output (OUT).
All IN pins must be connected together and to the power source. A ceramic bypass capacitor close to the device from IN to GND is recommended to alleviate bus transients. The recommended operating voltage range is 2.7 V-18 V.
Similarly all OUT pins must be connected together and to the load. V(OUT) in the ON condition, is calculated using Equation 9.
where, RON is the total ON resistance of the internal FET.
GND terminal is the most negative voltage in the circuit and is used as a reference for all voltage reference unless otherwise specified.