SLVSCE9D June   2014  – October  2017 TPS25942A , TPS25942L , TPS25944A , TPS25944L

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Enable and Adjusting Undervoltage Lockout
      2. 9.3.2  Overvoltage Protection (OVP)
      3. 9.3.3  Hot Plug-In and In-Rush Current Control
      4. 9.3.4  Overload and Short Circuit Protection
        1. 9.3.4.1 Overload Protection
        2. 9.3.4.2 Short Circuit Protection
        3. 9.3.4.3 Start-Up With Short on Output
        4. 9.3.4.4 Constant Current Limit Behavior During Overcurrent Faults
      5. 9.3.5  Reverse Current Protection
      6. 9.3.6  FAULT Response
      7. 9.3.7  Current Monitoring
      8. 9.3.8  Power Good Comparator
      9. 9.3.9  IN, OUT and GND Pins
      10. 9.3.10 Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Diode Mode
      2. 9.4.2 Shutdown Control
      3. 9.4.3 Operational Differences Between the TPS25942 and TPS25944
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Step by Step Design Procedure
        2. 10.2.2.2 Programming the Current-Limit Threshold: R(ILIM) Selection
        3. 10.2.2.3 Undervoltage Lockout and Overvoltage Set Point
        4. 10.2.2.4 Programming Current Monitoring Resistor—RIMON
        5. 10.2.2.5 Setting Output Voltage Ramp Time (tdVdT)
          1. 10.2.2.5.1 Case1: Start-Up Without Load: Only Output Capacitance C(OUT) Draws Current During Start-Up
          2. 10.2.2.5.2 Case 2: Start-Up With Load: Output Capacitance C(OUT) and Load Draws Current During Start-Up
        6. 10.2.2.6 Programing the Power Good Set Point
        7. 10.2.2.7 Support Component Selections—R6, R7 and CIN
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 Active ORing (Auto-Power Multiplexer) Operation
        1. 10.3.1.1 N+1 Power Supply Operation
        2. 10.3.1.2 Priority Power MUX Operation
        3. 10.3.1.3 Priority MUXing With Almost Equal Rails (VIN1 ~ VIN2)
        4. 10.3.1.4 Reverse Polarity Protection
  11. 11Power Supply Recommendations
    1. 11.1 Transient Protection
    2. 11.2 Output Short-Circuit Measurements
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Related Links
    4. 13.4 Receiving Notification of Documentation Updates
    5. 13.5 Community Resources
    6. 13.6 Trademarks
    7. 13.7 Electrostatic Discharge Caution
    8. 13.8 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.2.2.3 Undervoltage Lockout and Overvoltage Set Point

The undervoltage lockout (UVLO) and overvoltage trip point are adjusted using the external voltage divider network of R1, R2 and R3 as connected between IN, EN, OVP and GND pins of the TPS25942, TPS25944 devices. The values required for setting the undervoltage and overvoltage are calculated solving Equation 11 and Equation 12.

Equation 11. TPS25942A TPS25942L TPS25944A TPS25944L eq_10_slvsce9.gif

where

  • V(OVPR) = OVP Threshold for rising voltage
Equation 12. TPS25942A TPS25942L TPS25944A TPS25944L eq_11_slvsce9.gif

where

  • V(ENR) = Enable threshold for rising voltage

For minimizing the input current drawn from the power supply {I(R123) = V(IN)/(R1 + R2 + R3)}, it is recommended to use higher values of resistance for R1, R2 and R3.

However, leakage currents due to external active components connected to the resistor string can add error to these calculations. So, the resistor string current, I(R123) must be chosen to be 20x greater than the leakage current expected.

From the device electrical specifications, V(OVPR) = 0.99 V and V(ENR) = 0.99 V. For design requirements, V(OV) is 16.5 V and V(UV) is 10.8 V. To solve the equation, first choose the value of R3 = 31.2 kΩ and use Equation 11 to solve for (R1 + R2) = 488.8 kΩ. Use Equation 12 and value of (R1 + R2) to solve for R2 = 16.47 kΩ and finally R1= 472.33 kΩ.

Using the closest standard 1% resistor values gives R1 = 475 kΩ, R2 = 16.7 kΩ, and R3 = 31.2 kΩ.

The power fail threshold V(PFAIL) is detected on the falling edge of the power supply. The falling voltage threshold is 7% lower than the rising voltage threshold, so for a set V(UV) the power fail voltage V(PFAIL) is given by Equation 13.

Equation 13. V(PFAIL) = 0.93 x V(UV)