SLVSCE9D June   2014  – October  2017 TPS25942A , TPS25942L , TPS25944A , TPS25944L

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Enable and Adjusting Undervoltage Lockout
      2. 9.3.2  Overvoltage Protection (OVP)
      3. 9.3.3  Hot Plug-In and In-Rush Current Control
      4. 9.3.4  Overload and Short Circuit Protection
        1. 9.3.4.1 Overload Protection
        2. 9.3.4.2 Short Circuit Protection
        3. 9.3.4.3 Start-Up With Short on Output
        4. 9.3.4.4 Constant Current Limit Behavior During Overcurrent Faults
      5. 9.3.5  Reverse Current Protection
      6. 9.3.6  FAULT Response
      7. 9.3.7  Current Monitoring
      8. 9.3.8  Power Good Comparator
      9. 9.3.9  IN, OUT and GND Pins
      10. 9.3.10 Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Diode Mode
      2. 9.4.2 Shutdown Control
      3. 9.4.3 Operational Differences Between the TPS25942 and TPS25944
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Step by Step Design Procedure
        2. 10.2.2.2 Programming the Current-Limit Threshold: R(ILIM) Selection
        3. 10.2.2.3 Undervoltage Lockout and Overvoltage Set Point
        4. 10.2.2.4 Programming Current Monitoring Resistor—RIMON
        5. 10.2.2.5 Setting Output Voltage Ramp Time (tdVdT)
          1. 10.2.2.5.1 Case1: Start-Up Without Load: Only Output Capacitance C(OUT) Draws Current During Start-Up
          2. 10.2.2.5.2 Case 2: Start-Up With Load: Output Capacitance C(OUT) and Load Draws Current During Start-Up
        6. 10.2.2.6 Programing the Power Good Set Point
        7. 10.2.2.7 Support Component Selections—R6, R7 and CIN
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 Active ORing (Auto-Power Multiplexer) Operation
        1. 10.3.1.1 N+1 Power Supply Operation
        2. 10.3.1.2 Priority Power MUX Operation
        3. 10.3.1.3 Priority MUXing With Almost Equal Rails (VIN1 ~ VIN2)
        4. 10.3.1.4 Reverse Polarity Protection
  11. 11Power Supply Recommendations
    1. 11.1 Transient Protection
    2. 11.2 Output Short-Circuit Measurements
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Related Links
    4. 13.4 Receiving Notification of Documentation Updates
    5. 13.5 Community Resources
    6. 13.6 Trademarks
    7. 13.7 Electrostatic Discharge Caution
    8. 13.8 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Case 2: Start-Up With Load: Output Capacitance C(OUT) and Load Draws Current During Start-Up

When load draws current during the turn-on sequence, there is additional power dissipated. Considering a resistive load RL(SU) during start-up, load current ramps up proportionally with increase in output voltage during tdVdT time. Typical ramp-up of output voltage, load current and power dissipated in the device is shown in Figure 58 and power dissipation with respect to time is plotted in Figure 59. The additional power dissipation during start-up phase is calculated as follows shown in Equation 18 and Equation 19.

Equation 18. TPS25942A TPS25942L TPS25944A TPS25944L eq_16_slvsce9.gif
Equation 19. TPS25942A TPS25942L TPS25944A TPS25944L eq_17_slvsce9.gif

Where RL(SU) is the load resistance present during start-up. Average energy loss in internal FET during charging time due to resistive load is given by Equation 20.

Equation 20. TPS25942A TPS25942L TPS25944A TPS25944L eq_18_slvsce9.gif
TPS25942A TPS25942L TPS25944A TPS25944L Typical_start_up_with_Load.png
V(IN) = 12 V C(dVdT) = 1 nF, C(OUT) = 100 µF RL(SU) = 4.8 Ω
Figure 58. Typical Start-Up With Load
TPS25942A TPS25942L TPS25944A TPS25944L C060_SLVSCF3.png
V(IN) = 12 V C(dVdT) = 1 nF, C(OUT) = 100 µF RL(SU) = 4.8 Ω
Figure 59. PD(LOAD) in Load During Start-Up

Solving Equation 20 the average power loss in the device due to load is given by Equation 21.

Equation 21. TPS25942A TPS25942L TPS25944A TPS25944L eq_19_slvsce9.gif

Total power dissipated in the device during start-up is given by Equation 22.

Equation 22. TPS25942A TPS25942L TPS25944A TPS25944L eq_20_slvsce9.gif

Total current during start-up is given by Equation 23.

Equation 23. TPS25942A TPS25942L TPS25944A TPS25944L eq_21_slvsce9.gif

If I(STARTUP) > I(LIM), the device limits the current to I(LIM) and the current limited charging time is determined by Equation 24.

Equation 24. TPS25942A TPS25942L TPS25944A TPS25944L eq_22_slvsce9.gif

The power dissipation, with and without load, for selected start-up time must not exceed the shutdown limits as shown in Figure 60.

For the design example under discussion,

Select ramp-up capacitor C(dVdT) = 1nF, using Equation 2, we get Equation 25.

Equation 25. TPS25942A TPS25942L TPS25944A TPS25944L eq_23_slvsce9.gif

The inrush current drawn by the load capacitance (C(OUT)) during ramp-up is calculated using Equation 3 and Equation 26.

Equation 26. TPS25942A TPS25942L TPS25944A TPS25944L eq_24_slvsce9.gif

The inrush Power dissipation is calculated, using Equation 17 and Equation 27.

Equation 27. TPS25942A TPS25942L TPS25944A TPS25944L eq_25_slvsce9.gif

For 7.2 W of power loss, the thermal shut down time of the device must not be less than the ramp-up time tdVdT to avoid the false trip at maximum operating temperature. From thermal shutdown limit graph Figure 60 at TA = 85°C, for 7.2 W of power the shutdown time is approximately 60 ms. So it is safe to use 1 ms as start-up time without any load on output.

Considering the start-up with load 4.8 Ω, the additional power dissipation, when load is present during start-up is calculated, using Equation 21 and Equation 28.

Equation 28. TPS25942A TPS25942L TPS25944A TPS25944L eq_26_slvsce9.gif

The total device power dissipation during start up is given by Equation 29.

Equation 29. TPS25942A TPS25942L TPS25944A TPS25944L eq_27_slvsce9.gif

From thermal shutdown limit graph at TA = 85°C, the thermal shutdown time for 12.2 W is close to 7.5 ms. It is safe to have 30% margin to allow for variation of system parameters such as load, component tolerance, and input voltage. So it is well within acceptable limits to use the 1 nF capacitor with start-up load of 4.8 Ω.

If there is a need to decrease the power loss during start-up, it can be done with increase of C(dVdT) capacitor.

To illustrate, choose C(dVdT) = 1.5 nF as an option and recalculate as shown in Equation 30 to Equation 34.

Equation 30. TPS25942A TPS25942L TPS25944A TPS25944L eq_28_slvsce9.gif
Equation 31. TPS25942A TPS25942L TPS25944A TPS25944L eq_29_slvsce9.gif
Equation 32. TPS25942A TPS25942L TPS25944A TPS25944L eq_30_slvsce9.gif
Equation 33. TPS25942A TPS25942L TPS25944A TPS25944L eq_31_slvsce9.gif
Equation 34. TPS25942A TPS25942L TPS25944A TPS25944L eq_32_slvsce9.gif

From thermal shutdown limit graph at TA = 85°C, the shutdown time for 10 W power dissipation is approximately 17 ms, which increases the margins further for shutdown time and ensures successful operation during start-up and steady state conditions.

The spreadsheet tool available on the web can be used for iterative calculations.