SLVSGG5C november   2021  – april 2023 TPS2597

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Undervoltage Lockout (UVLO and UVP)
      2. 8.3.2 Overvoltage Lockout (OVLO)
      3. 8.3.3 Overvoltage Clamp (OVC)
      4. 8.3.4 Inrush Current, Overcurrent, and Short Circuit Protection
        1. 8.3.4.1 Slew Rate (dVdt) and Inrush Current Control
        2. 8.3.4.2 Circuit-Breaker
        3. 8.3.4.3 Active Current Limiting
        4. 8.3.4.4 Short-Circuit Protection
      5. 8.3.5 Analog Load Current Monitor
      6. 8.3.6 Overtemperature Protection (OTP)
      7. 8.3.7 Fault Response and Indication (FLT)
      8. 8.3.8 Power-Good Indication (PG)
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Single Device, Self-Controlled
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Device Selection
        2. 9.2.2.2 Setting Undervoltage and Overvoltage Thresholds
        3. 9.2.2.3 Setting Output Voltage Rise Time (tR)
        4. 9.2.2.4 Setting Power-Good Assertion Threshold
        5. 9.2.2.5 Setting Overcurrent Threshold (ILIM)
        6. 9.2.2.6 Setting Overcurrent Blanking Interval (tITIMER)
      3. 9.2.3 Application Curves
    3. 9.3 Parallel Operation
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Transient Protection
      2. 9.4.2 Output Short-Circuit Measurements
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.5.1 Layout Guidelines

  • For all applications, TI recommends a ceramic decoupling capacitor of 0.1 μF or greater between the IN terminal and GND terminal.
  • The optimal placement of the decoupling capacitor is closest to the IN and GND terminals of the device. Care must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the GND terminal of the IC.
  • High current-carrying power-path connections must be as short as possible and must be sized to carry at least twice the full-load current.
  • The GND terminal must be tied to the PCB ground plane at the terminal of the IC with the shortest possible trace. The PCB ground must be a copper plane or island on the board. TI recommends to have a separate ground plane island for the eFuse. This plane does not carry any high currents and serves as a quiet ground reference for all the critical analog signals of the eFuse. The device ground plane must be connected to the system power ground plane using a star connection.
  • The IN and OUT pins are used for heat dissipation. Connect to as much copper area on top and bottom PCB layers using as possible with thermal vias. The vias under the device also help to minimize the voltage gradient across the IN and OUT pads and distribute current uniformly through the device, which is essential to achieve the best on-resistance and current sense accuracy.
  • Locate the following support components close to their connection pins:

    • RILM

    • CdVdT

    • CITIMER

    • Resistors for the EN/UVLO, OVLO/OVCSEL, and PGTH pins
  • Connect the other end of the component to the GND pin of the device with shortest trace length. The trace routing for the RILM, CITIMER and CdVdt components to the device must be as short as possible to reduce parasitic effects on the current limit, overcurrent blanking interval and soft start timing. It's recommended to keep parasitic capacitance on ILM pin below 50 pF to ensure stable operation. These traces must not have any coupling to switching signals on the board.
  • Because the bias current on ILM pin directly controls the overcurrent protection behavior of the device, the PCB routing of this node must be kept away from any noisy (switching) signals.
  • Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the device they are intended to protect. These protection devices must be routed with short traces to reduce inductance. For example, TI recommends a protection Schottky diode to address negative transients due to switching of inductive loads. TI also recommends to add a ceramic decoupling capacitor of 1 μF or greater between OUT and GND. These components must be physically close to the OUT pins. Care must be taken to minimize the loop area formed by the Schottky diode/bypass-capacitor connection, the OUT pin, and the GND terminal of the IC.