The IN Exposed Thermal Pad is used for Heat Dissipation. Connect to as much copper area as possible using an array of thermal vias. The via array also helps to minimize the voltage gradient across the VIN pad and facilitates uniform current distribution through the internal FET, which improves the current sensing and monitoring accuracy.
For all applications, TI recommends a ceramic decoupling capacitor of 0.01 μF or greater between IN and GND terminals. For hot-plug applications, where input power-path inductance is negligible, this capacitor can be eliminated or minimized.
The optimal placement of the decoupling capacitor is closest to the IN and GND terminals of the device. Care must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the GND terminal of the IC.
High current carrying power path connections must be as short as possible and must be sized to carry at least twice the full-load current. It is recommended to use a minimum trace width of 50 mil for the OUT power connection.
The GND terminal is the reference for all internal signals and must be isolated from any bounce due to large switching currents in the system power ground plane. It is recommended to connect the device GND to a signal ground island on the board, which in turn is connected to the system power GND plane at one point.
Locate the support components for the following signals close to their respective connection pins - ILIM, IMON, ITIMER, RETRY_DLY, NRETRY and dVdT with the shortest possible trace routing to reduce parasitic effects on the respective associated functions. These traces must not have any coupling to switching signals on the board.
The ILIM pin is highly sensitive to capacitance and TI recommends to pay special attention to the layout to maintain the parasitic capacitance below 30 pF for stable operation.
Use short traces on the RETRY_DLY and NRETRY pins to ensure the auto-retry timer delay and number of auto-retries is not altered by the additional parasitic capacitance on these pins.
Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the device they are intended to protect. These protection devices must be routed with short traces to reduce inductance. For example, TI recommends a protection Schottky diode to address negative transients due to switching of inductive loads, and it must be physically close to the OUT pins.
Use proper layout and thermal management techniques to ensure there is no significant steady state thermal gradient between the two thermal pads on the IC. This is necessary for proper functioning of the device overtemperature protection mechanism and successful startup under all conditions.
Obtaining acceptable performance with alternate layout schemes is possible; the Layout Example is intended as a guideline and shown to produce good results from electrical and thermal standpoint.