SLVSGG6B april   2022  – june 2023 TPS25981

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
      1.      16
    8. 7.8 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Undervoltage Lockout (UVLO and UVP)
      2. 8.3.2 Overvoltage Lockout (OVLO)
      3. 8.3.3 Inrush Current, Overcurrent, and Short-Circuit Protection
        1. 8.3.3.1 Slew Rate (dVdt) and Inrush Current Control
        2. 8.3.3.2 Circuit-Breaker During Steady-State
        3. 8.3.3.3 Active Current Limiting During Start-Up
        4. 8.3.3.4 Short-Circuit Protection
      4. 8.3.4 Analog Load Current Monitor
      5. 8.3.5 Overtemperature Protection (OTP)
      6. 8.3.6 Fault Response and Indication (FLT)
      7. 8.3.7 Power Good Indication (PG)
      8. 8.3.8 Quick Output Discharge (QOD)
      9. 8.3.9 Reverse Current Blocking FET Driver
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Single Device, Self-Controlled
      2. 9.1.2 Parallel Operation
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Device Selection
        2. 9.2.2.2 Setting Output Voltage Rise Time (tR)
        3. 9.2.2.3 Setting Overcurrent Threshold (ILIM)
        4. 9.2.2.4 Setting Overcurrent Blanking Interval (tITIMER)
        5. 9.2.2.5 Voltage Drop
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
    1. 10.1 Transient Protection
    2. 10.2 Output Short-Circuit Measurements
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4 Thermal Information

THERMAL METRIC (1) TPS25981xx UNIT
RPW (QFN)
10 PINS
RθJA Junction-to-ambient thermal resistance 49.7(2) °C/W
71.8(3) °C/W
RθJB Junction-to-board thermal resistance 15.7 °C/W
ΨJT Junction-to-top characterization parameter 2.1(2) °C/W
Junction-to-top characterization parameter 1.3(3) °C/W
ΨJB Junction-to-board characterization parameter 23 (2) °C/W
14.5 (3) °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) Based on simulations conducted with the device mounted on a custom 4-layer PCB (2s2p) with 8 thermal vias under device
(3) Based on simulations conducted with the device mounted on a JEDEC 4-layer PCB (2s2p) with no thermal vias under device