SLVSGX1A July   2023  – October 2023 TPS25984

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Description (continued)
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Logic Interface
    7. 7.7 Timing Requirements
    8. 7.8 Switching Characteristics
    9. 7.9 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Undervoltage Protection
      2. 8.3.2  Insertion Delay
      3. 8.3.3  Overvoltage Protection
      4. 8.3.4  Inrush Current, Overcurrent, and Short-Circuit Protection
        1. 8.3.4.1 Slew Rate (dVdt) and Inrush Current Control
          1. 8.3.4.1.1 Start-Up Time Out
        2. 8.3.4.2 Steady-State Overcurrent Protection (Circuit-Breaker)
        3. 8.3.4.3 Active Current Limiting During Start-Up
        4. 8.3.4.4 Short-Circuit Protection
      5. 8.3.5  Analog Load Current Monitor (IMON)
      6. 8.3.6  Mode Selection (MODE)
      7. 8.3.7  Parallel Device Synchronization (SWEN)
      8. 8.3.8  Stacking Multiple eFuses for Unlimited Scalability
        1. 8.3.8.1 Current Balancing During Start-Up
      9. 8.3.9  Analog Junction Temperature Monitor (TEMP)
      10. 8.3.10 Overtemperature Protection
      11. 8.3.11 Fault Response and Indication (FLT)
      12. 8.3.12 Power-Good Indication (PG)
      13. 8.3.13 Output Discharge
      14. 8.3.14 FET Health Monitoring
      15. 8.3.15 Single Point Failure Mitigation
        1. 8.3.15.1 IMON Pin Single Point Failure
        2. 8.3.15.2 ILIM Pin Single Point Failure
        3. 8.3.15.3 IREF Pin Single Point Failure
        4. 8.3.15.4 ITIMER Pin Single Point Failure
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Single Device, Standalone Operation
      2. 9.1.2 Multiple Devices, Parallel Connection
      3. 9.1.3 Multiple eFuses, Parallel Connection With PMBus
      4. 9.1.4 Digital Telemetry Using External Microcontroller
    2. 9.2 Typical Application: 12-V, 3.3-kW Power Path Protection in Data Center Servers
      1. 9.2.1 Application
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
    3. 9.3 Best Design Practices
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Transient Protection
      2. 9.4.2 Output short-Circuit Measurements
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
8.3.4.1.1 Start-Up Time Out

If the start-up is not completed, that is, the FET is not fully turned on within a certain timeout interval (tSU_TMR) after SWEN is asserted, the device registers it as a fault. FLT is asserted low and the device goes into latch-off or auto-retry mode depending on the device configuration.