SLVSGX1A
July 2023 – October 2023
TPS25984
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Revision History
5
Description (continued)
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Logic Interface
7.7
Timing Requirements
7.8
Switching Characteristics
7.9
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Undervoltage Protection
8.3.2
Insertion Delay
8.3.3
Overvoltage Protection
8.3.4
Inrush Current, Overcurrent, and Short-Circuit Protection
8.3.4.1
Slew Rate (dVdt) and Inrush Current Control
8.3.4.1.1
Start-Up Time Out
8.3.4.2
Steady-State Overcurrent Protection (Circuit-Breaker)
8.3.4.3
Active Current Limiting During Start-Up
8.3.4.4
Short-Circuit Protection
8.3.5
Analog Load Current Monitor (IMON)
8.3.6
Mode Selection (MODE)
8.3.7
Parallel Device Synchronization (SWEN)
8.3.8
Stacking Multiple eFuses for Unlimited Scalability
8.3.8.1
Current Balancing During Start-Up
8.3.9
Analog Junction Temperature Monitor (TEMP)
8.3.10
Overtemperature Protection
8.3.11
Fault Response and Indication (FLT)
8.3.12
Power-Good Indication (PG)
8.3.13
Output Discharge
8.3.14
FET Health Monitoring
8.3.15
Single Point Failure Mitigation
8.3.15.1
IMON Pin Single Point Failure
8.3.15.2
ILIM Pin Single Point Failure
8.3.15.3
IREF Pin Single Point Failure
8.3.15.4
ITIMER Pin Single Point Failure
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.1.1
Single Device, Standalone Operation
9.1.2
Multiple Devices, Parallel Connection
9.1.3
Multiple eFuses, Parallel Connection With PMBus
9.1.4
Digital Telemetry Using External Microcontroller
9.2
Typical Application: 12-V, 3.3-kW Power Path Protection in Data Center Servers
9.2.1
Application
9.2.2
Design Requirements
9.2.3
Detailed Design Procedure
9.2.4
Application Curves
9.3
Best Design Practices
9.4
Power Supply Recommendations
9.4.1
Transient Protection
9.4.2
Output short-Circuit Measurements
9.5
Layout
9.5.1
Layout Guidelines
9.5.2
Layout Example
10
Device and Documentation Support
10.1
Documentation Support
10.1.1
Related Documentation
10.2
Support Resources
10.3
Trademarks
10.4
Electrostatic Discharge Caution
10.5
Glossary
11
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RZJ|32
MPQF664A
Thermal pad, mechanical data (Package|Pins)
RZJ|32
QFND783
Orderable Information
slvsgx1a_oa
slvsgx1a_pm
1
Features
Input operating voltage range: 4.5 V to 16 V
Absolute maximum: 20 V
Withstands negative voltages up to –1 V at output
Integrated FET with ultra-low on-resistance: 0.8 mΩ (typical)
Rated for RMS current of 55 A and peak current of 70 A
Supports parallel connection of multiple eFuses for higher current support
Active device state synchronization and load sharing during start-up and steady-state
Robust overcurrent protection
Adjustable overcurrent threshold (I
OCP
): 10 A to 55 A with accuracy of ±5%
Circuit-breaker response during steady state operation with adjustable transient overcurrent timer (ITIMER) to support peak currents up to 2 × I
OCP
Adjustable active current limit during start-up (I
LIM
)
Robust short-circuit protection
Fast-trip response (< 200 ns) to output short-circuit events
Adjustable threshold (2 × I
OCP
)
Immune to supply line transients — no nuisance tripping
Precise analog load current monitoring
Accuracy: ±1.4 %
Bandwidth: > 500 kHz
Fast overvoltage protection (fixed 16.7-V threshold)
Adjustable output slew rate control (dVdt) for inrush current protection
Active high enable input with adjustable undervoltage lockout (UVLO)
Overtemperature Protection (OTP) to ensure FET SOA
Guaranteed FET SOA: 10 W√s
Integrated FET health monitoring and reporting
Analog die temperature monitor output (TEMP)
Dedicated fault indication pin (
FLT
)
Power-Good indication pin (PG)
Small footprint: QFN 5 mm × 5 mm
100% Pb free