SLVSGG3A May   2022  – September 2022 TPS25985

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Logic Interface
    7. 7.7 Timing Requirements
    8. 7.8 Switching Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Undervoltage Protection
      2. 8.3.2  Insertion Delay
      3. 8.3.3  Overvoltage Protection
      4. 8.3.4  Inrush Current, Overcurrent, and Short-Circuit Protection
        1. 8.3.4.1 Slew rate (dVdt) and Inrush Current Control
          1. 8.3.4.1.1 Start-Up Time Out
        2. 8.3.4.2 Steady-State Overcurrent Protection (Circuit-Breaker)
        3. 8.3.4.3 Active Current Limiting During Start-Up
        4. 8.3.4.4 Short-Circuit Protection
      5. 8.3.5  Analog Load Current Monitor (IMON)
      6. 8.3.6  Mode Selection (MODE)
      7. 8.3.7  Parallel Device Synchronization (SWEN)
      8. 8.3.8  Stacking Multiple eFuses for Unlimited Scalability
        1. 8.3.8.1 Current Balancing During Start-Up
      9. 8.3.9  Analog Junction Temperature Monitor (TEMP)
      10. 8.3.10 Overtemperature Protection
      11. 8.3.11 Fault Response and Indication (FLT)
      12. 8.3.12 Power Good Indication (PG)
      13. 8.3.13 Output Discharge
      14. 8.3.14 General Purpose Comparator
      15. 8.3.15 FET Health Monitoring
      16. 8.3.16 Single Point Failure Mitigation
        1. 8.3.16.1 IMON Pin Single Point Failure
        2. 8.3.16.2 ILIM Pin Single Point Failure
        3. 8.3.16.3 IREF Pin Single Point Failure
        4. 8.3.16.4 ITIMER Pin Single Point Failure
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Single Device, Standalone Operation
      2. 9.1.2 Multiple Devices, Parallel Connection
    2. 9.2 Typical Application: 12-V, 3.6-kW Power Path Protection in Datacenter Servers
      1. 9.2.1 Application
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Performance Plots
    3. 9.3 Multiple eFuses, Parallel Connection with PMBus
    4. 9.4 Digital Telemetry Using External Microcontroller
    5. 9.5 What to Do and What Not to Do
  10. 10Power Supply Recommendations
    1. 10.1 Transient Protection
    2. 10.2 Output Short-Circuit Measurements
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.9 Typical Characteristics

Figure 7-1 ON Resistance Across Temperature
Figure 7-3 VIN Undervoltage Thresholds Across Temperature
Figure 7-5 EN/UVLO Thresholds Across Temperature
Figure 7-7 IREF Charging Current Across Temperature
Figure 7-9 IMON Gain Accuracy Across Load and Temperature
Figure 7-11 Steady-State Overcurrent Protection Threshold (Circuit-Breaker) Accuracy
Figure 7-13 Backup Overcurrent Protection Threshold (Start-up) Accuracy
Figure 7-15 ITIMER Pin Internal Pullup Voltage Across Temperature
Figure 7-17 ITIMER Pin Discharge Differential Voltage Threshold Across Temperature
Figure 7-19 DVDT Charging Current Across Temperature
Figure 7-21 QOD Sink Current Across Temperature
Figure 7-23 Junction Temperature vs Load Current (TA = 25°C, With Air-Flow)
GUID-20220514-SS0I-KL81-KW4Z-VNRH9448LPKF-low.gif
Input supply held steady, EN/UVLO pin toggled high and low
Figure 7-25 Power Up and Down Sequencing Using EN/UVLO Pin
GUID-20220514-SS0I-PC1J-PCDK-2G3H5T97THHG-low.gif
COUT = 6.8 mF, CdVdt = 33 nF
Figure 7-27 Inrush Current Control with Capacitive Load
GUID-20220514-SS0I-NNLX-9JLZ-06FSXHX2VWXT-low.gif
Input supply ramped up above 16.6 V
Figure 7-29 Input Overvoltage Protection Response
GUID-20220514-SS0I-MP5T-QH91-2VMKRSNHMB00-low.gif
IOCP = 50 A, tITIMER = 14 ms, IOUT stays above the IOCP threshold persistently to trigger circuit-breaker response
Figure 7-31 Overcurrent Protection Response (Circuit-Breaker)
GUID-20220514-SS0I-VWG3-1WW3-N6WP6XDG6636-low.gif
Device turned on using SWEN with output hard-short to GND. Device limits the current with foldback.
Figure 7-33 Power Up into Short-Circuit
Figure 7-2 VDD Undervoltage Thresholds Across Temperature
Figure 7-4 Overvoltage Protection Threshold Across Temperature
Figure 7-6 EN/UVLO Based Shutdown Falling Threshold Across Temperature
Figure 7-8 IMON Gain Across Load and Temperature
Figure 7-10 IMON Gain Accuracy Across Process and Temperature Corners
Figure 7-12 Start-up Overcurrent Protection Threshold (Current Limit) Accuracy
Figure 7-14 Backup Overcurrent Protection Threshold (Steady-State) Accuracy
Figure 7-16 ITIMER Pin Discharge Current Across Temperature
Figure 7-18 SWEN Pin Logic Thresholds Across Temperature
Figure 7-20 DVDT Gain Across Temperature
Figure 7-22 Junction Temperature vs Load Current (No Air-Flow)
GUID-20220514-SS0I-2HD4-3XJ8-HV1TCFZT5XDR-low.gif
EN held high, input supply ramped up and down
Figure 7-24 Power Up and Down Sequencing Using Input Supply
GUID-20220514-SS0I-67XP-9VLK-6N9PWQCN7R6G-low.gif
Input supply held steady, EN/UVLO pin held high, SWEN pin toggled high and low
Figure 7-26 Power Up and Down Sequencing Using SWEN Pin
GUID-20220514-SS0I-1CNV-TC3T-ZPFFZVVNVGPG-low.gif
COUT = 6.8 mF, ROUT = 1.2 Ω, CdVdt = 33 nF
Figure 7-28 Inrush Current Control with Capacitive and Resistive Load
GUID-20220514-SS0I-LTT1-B9MS-QNNT9Q8FLB7R-low.gif
IOCP = 50 A, tITIMER = 14 ms, IOUT pulsed above the IOCP threshold for short duration without triggering circuit-breaker response
Figure 7-30 Peak Current Support Using Transient Overcurrent Blanking
GUID-20220514-SS0I-BQ34-M89M-BKHNQLBZBSFN-low.gif
IOCP = 50 A, Output hard-short to GND while in steady. IOUT rises above 2 × IOCP triggers fast-trip response
Figure 7-32 Short-Circuit Protection Response