SLVSGG3A May   2022  – September 2022 TPS25985

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Logic Interface
    7. 7.7 Timing Requirements
    8. 7.8 Switching Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Undervoltage Protection
      2. 8.3.2  Insertion Delay
      3. 8.3.3  Overvoltage Protection
      4. 8.3.4  Inrush Current, Overcurrent, and Short-Circuit Protection
        1. 8.3.4.1 Slew rate (dVdt) and Inrush Current Control
          1. 8.3.4.1.1 Start-Up Time Out
        2. 8.3.4.2 Steady-State Overcurrent Protection (Circuit-Breaker)
        3. 8.3.4.3 Active Current Limiting During Start-Up
        4. 8.3.4.4 Short-Circuit Protection
      5. 8.3.5  Analog Load Current Monitor (IMON)
      6. 8.3.6  Mode Selection (MODE)
      7. 8.3.7  Parallel Device Synchronization (SWEN)
      8. 8.3.8  Stacking Multiple eFuses for Unlimited Scalability
        1. 8.3.8.1 Current Balancing During Start-Up
      9. 8.3.9  Analog Junction Temperature Monitor (TEMP)
      10. 8.3.10 Overtemperature Protection
      11. 8.3.11 Fault Response and Indication (FLT)
      12. 8.3.12 Power Good Indication (PG)
      13. 8.3.13 Output Discharge
      14. 8.3.14 General Purpose Comparator
      15. 8.3.15 FET Health Monitoring
      16. 8.3.16 Single Point Failure Mitigation
        1. 8.3.16.1 IMON Pin Single Point Failure
        2. 8.3.16.2 ILIM Pin Single Point Failure
        3. 8.3.16.3 IREF Pin Single Point Failure
        4. 8.3.16.4 ITIMER Pin Single Point Failure
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Single Device, Standalone Operation
      2. 9.1.2 Multiple Devices, Parallel Connection
    2. 9.2 Typical Application: 12-V, 3.6-kW Power Path Protection in Datacenter Servers
      1. 9.2.1 Application
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Performance Plots
    3. 9.3 Multiple eFuses, Parallel Connection with PMBus
    4. 9.4 Digital Telemetry Using External Microcontroller
    5. 9.5 What to Do and What Not to Do
  10. 10Power Supply Recommendations
    1. 10.1 Transient Protection
    2. 10.2 Output Short-Circuit Measurements
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.4.2 Steady-State Overcurrent Protection (Circuit-Breaker)

The TPS25985x responds to output overcurrent conditions during steady-state by performing a circuit-breaker action after a user-adjustable transient fault blanking interval. This action allows the device to support a higher peak current for a short user-defined interval but also ensures robust protection in case of persistent output faults.

The device constantly senses the output load current and provides an analog current output (IIMON) on the IMON pin which is proportional to the load current, which in turn produces a proportional voltage (VIMON) across the IMON pin resistor (RIMON) as per Equation 4.

Equation 4. VIMON=IOUT×GIMON×RIMON
Where GIMON is the current monitor gain (IIMON : IOUT)

The overcurrent condition is detected by comparing this voltage against the voltage on the IREF pin as a reference. The reference voltage (VIREF) can be controlled in two ways, which sets the overcurrent protection threshold (IOCP) accordingly.

  • In the standalone or primary mode of operation, the internal current source interacts with the external IREF pin resistor (RIREF) to generate the reference voltage. It is also possible to drive the IREF pin from an external low impedance reference voltage source as shown in Equation 5.
    Equation 5. VIREF=IIREF×RIREF
  • In a primary and secondary parallel configuration, the primary eFuse or controller drives the voltage on the IREF pin to provide an external reference (VIREF) for all the secondary devices in the chain.

The overcurrent protection threshold during steady-state (IOCP) can be calculated using Equation 6.

Equation 6. IOCP=VIREFGIMON×RIMON

Note:

Maintain VIREF within the recommended voltage range to ensure proper operation of the overcurrent detection circuit.

TI recommends to add a 150-pF capacitor from IREF pin to GND for improved noise immunity.

After an overcurrent condition is detected, that is the load current exceeds the programmed current limit threshold (IOCP), but stays lower than the short-circuit threshold (2 × IOCP), the device starts discharging the ITIMER pin capacitor using an internal 2.07-μA pulldown current. If the load current drops below the current limit threshold before the ITIMER capacitor discharges by ΔVITIMER, the ITIMER is reset by pulling it up to VINT internally and the circuit-breaker action is not engaged. This action allows short overload transient pulses to pass through the device without tripping the circuit. If the overcurrent condition persists, the ITIMER capacitor continues to discharge and after it falls by ΔVITIMER, the circuit-breaker action turns off the FET immediately. At the same time, the ITIMER cap is charged up to VINT again so that it is at its default state before the next overcurrent event. This action ensures the full blanking timer interval is provided for every overcurrent event. Equation 43 can be used to calculate the RIMON value for the desired overcurrent threshold.

Equation 7. RIMON=VIREFGIMON×IOCP

The duration for which transients are allowed can be adjusted using an appropriate capacitor value from ITIMER pin to ground. The transient overcurrent blanking interval can be calculated using Equation 8.

Equation 8. tITIMERms=CITIMERnF×∆VITIMERVIITIMERμA

Note:

  1. Leave the ITIMER pin open to allow the part to break the circuit with the minimum possible delay. However, this makes the circuit-breaker response extremely sensitive to noise and can cause false tripping during load transients.

  2. Shorting the ITIMER pin to ground results in minimum overcurrent response delay (similar to ITIMER pin open condition), but increases the quiescent current – not a recommended mode of operation.

  3. Increasing the ITIMER cap value extends the overcurrent blanking interval. However, it also extends the time needed for the ITIMER cap to recharge up to VINT before the next overcurrent event. If the next overcurrent event occurs before the ITIMER cap is recharged fully, it takes less time to discharge to the VITIMER threshold, thereby it provides a shorter blanking interval than intended.

Figure 8-4 illustrates the overcurrent response for TPS25985x eFuse. After the part shuts down due to a circuit-breaker fault, it either stays latched off (TPS259850 variant) or restarts automatically after a fixed delay (TPS259851 variant).

GUID-20211230-SS0I-0SFS-H5DD-KQVCFB1PXQB5-low.gifFigure 8-4 Steady-State Overcurrent (Circuit-Breaker) Response