10.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:

• VIN and VOUT traces should be as short and wide as possible to accommodate for high current.
• The VIN pin should be bypassed to ground with low ESR ceramic bypass capacitors. The typical recommended bypass capacitance is 1-μF ceramic with X5R or X7R dielectric. This capacitor should be placed as close to the device pins as possible.
• The VOUT pin should be bypassed to ground with low ESR ceramic bypass capacitors. The typical recommended bypass capacitance is one-tenth of the VIN bypass capacitor of X5R or X7R dielectric rating. This capacitor should be placed as close to the device pins as possible.

10.2 Layout Example

Figure 23. Layout Example

10.3 Thermal Reliability

For higher reliability, TI recommends limiting the TPS27081A die junction temperature to less than 105°C. The device junction temperature is directly proportional to the ON-chip power dissipation. Use the following equation to calculate maximum ON-chip power dissipation to achieve the maximum die junction temperature target:

Equation 8.

where

• T_J(max) is the target maximum junction temperature
• T_A is the operating ambient temperature
• R_θJA is the package junction to ambient thermal resistance

10.4 Improving Package Thermal Performance

The package R_θJA value under standard conditions on a High-K board is listed in . R_θJA value depends on the PC board layout. An external heat sink and/or a cooling mechanism, like a cold air fan, can help reduce R_θJA and thus improve device thermal capabilities. Refer to TI’s design support web page at www.ti.com/thermal for a general guidance on improving device thermal performance.