SLVSF24C december   2020  – may 2023 TPS272C45

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
    1. 6.1 Recommended Connections for Unused Pins
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SNS Timing Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Programmable Current Limit
        1. 9.3.1.1 Inrush Current Handling
        2. 9.3.1.2 Calculating RILIMx
        3. 9.3.1.3 Configuring ILIMx From an MCU
      2. 9.3.2 Low Power Dissipation
      3. 9.3.3 Protection Mechanisms
        1. 9.3.3.1 Short-Circuit Protection
          1. 9.3.3.1.1 VS During Short-to-Ground
        2. 9.3.3.2 Inductive Load Demagnetization
        3. 9.3.3.3 Thermal Shutdown
        4. 9.3.3.4 Undervoltage Lockout on VS (UVLO)
        5. 9.3.3.5 Undervoltage Lockout on Low Voltage Supply (VDD_UVLO)
        6. 9.3.3.6 Power-Up and Power-Down Behavior
        7. 9.3.3.7 Overvoltage Protection (OVPR)
      4. 9.3.4 Diagnostic Mechanisms
        1. 9.3.4.1 Current Sense
          1. 9.3.4.1.1 RSNS Value
            1. 9.3.4.1.1.1 Current Sense Output Filter
        2. 9.3.4.2 Fault Indication
          1. 9.3.4.2.1 Fault Event Diagrams
        3. 9.3.4.3 Short-to-Supply or Open-Load Detection
          1. 9.3.4.3.1 Detection With Switch Enabled
          2. 9.3.4.3.2 Detection With Switch Disabled
        4. 9.3.4.4 Current Sense Resistor Sharing
    4. 9.4 Device Functional Modes
      1. 9.4.1 Off
      2. 9.4.2 Diagnostic
      3. 9.4.3 Active
      4. 9.4.4 Fault
  11. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 IEC 61000-4-5 Surge
      2. 10.1.2 Inverse Current
      3. 10.1.3 Loss of GND
      4. 10.1.4 Paralleling Channels
      5. 10.1.5 Thermal Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 RILIM Calculation
        2. 10.2.2.2 Diagnostics
          1. 10.2.2.2.1 Selecting the RISNS Value
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
9.3.4.2.1 Fault Event Diagrams
Note:

All timing diagrams assume that the SEL pin is low to measure channel one behavior on the SNS pin. DIA_EN and SEL pins have no effect on the FLT (versions A, B, C) or FLT1, FLT2 (version D) pin output.

The LATCH, SEL, DIA_EN, and ENx pins are controlled by the user. The timing diagrams represent possible use-cases.

Figure 9-12 shows the device fault reporting behavior in the event of a fault in channel 2 (only) with LATCH and SEL pin set to LO. As shown, the fault signaling is deactivated when EN is toggled (in this case from HI to LO to HI). The faulted channel can be determined by toggling the EN pin with a short pulse (less than 10-us wide) that does not affect the output of the channel.

GUID-FF43D04A-3067-428C-BF59-4F84E29DD112-low.svgFigure 9-12 FLT Pin Behavior (Versions A, B, C)

Figure 9-13 shows the device fault reporting behavior in the event of an overcurrent fault when EN goes high. As shown, the fault signaling is active only after the initial inrush current limit phase is complete.

GUID-20211124-SS0I-KBS8-RVJX-0WKJNWCTHHBZ-low.svgFigure 9-13 FLT Pin Behavior With an Overcurrent Event On Channel Enable (Versions A, B,C)

Figure 9-14 shows the device fault and retry behavior when there is a slow creep into an overcurrent event. As shown, the switch clamps the current until it hits thermal shutdown, and then the device remains latched off until the LATCH pin is low.

GUID-20211119-SS0I-SCWP-DK7S-SVVX6ZLQMCJW-low.svgFigure 9-14 Current Limit – Latched Behavior

Figure 9-15 shows the behavior with LATCH tied to GND; hence, the switch retries after the fault is cleared and tRETRY has expired.

GUID-20211119-SS0I-NMHG-GG4K-MLGQMR0GZQTP-low.svgFigure 9-15 Current Limit – LATCH = 0

When the switch retries after a shutdown event, the fault indication remains until VOUTx has risen to VVS – 1.8 V. After VOUTx has risen, the FLT output is reset and current sensing is available. If there is a short-to-ground and VOUT is not able to rise, the SNS fault indication remains indefinitely. Figure 9-16 illustrates auto-retry behavior and provides a zoomed-in view of the fault indication during retry.

Note:

Figure 9-16 assumes that tRETRY has expired by the time that TJ reaches the hysteresis threshold.

LATCH = LO and DIA_EN = HI

GUID-802640A5-3AE5-4C0A-BDF0-2C923B0731FF-low.svgFigure 9-16 Fault Indication During Retry