SLVSF24C december   2020  – may 2023 TPS272C45

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
    1. 6.1 Recommended Connections for Unused Pins
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SNS Timing Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Programmable Current Limit
        1. 9.3.1.1 Inrush Current Handling
        2. 9.3.1.2 Calculating RILIMx
        3. 9.3.1.3 Configuring ILIMx From an MCU
      2. 9.3.2 Low Power Dissipation
      3. 9.3.3 Protection Mechanisms
        1. 9.3.3.1 Short-Circuit Protection
          1. 9.3.3.1.1 VS During Short-to-Ground
        2. 9.3.3.2 Inductive Load Demagnetization
        3. 9.3.3.3 Thermal Shutdown
        4. 9.3.3.4 Undervoltage Lockout on VS (UVLO)
        5. 9.3.3.5 Undervoltage Lockout on Low Voltage Supply (VDD_UVLO)
        6. 9.3.3.6 Power-Up and Power-Down Behavior
        7. 9.3.3.7 Overvoltage Protection (OVPR)
      4. 9.3.4 Diagnostic Mechanisms
        1. 9.3.4.1 Current Sense
          1. 9.3.4.1.1 RSNS Value
            1. 9.3.4.1.1.1 Current Sense Output Filter
        2. 9.3.4.2 Fault Indication
          1. 9.3.4.2.1 Fault Event Diagrams
        3. 9.3.4.3 Short-to-Supply or Open-Load Detection
          1. 9.3.4.3.1 Detection With Switch Enabled
          2. 9.3.4.3.2 Detection With Switch Disabled
        4. 9.3.4.4 Current Sense Resistor Sharing
    4. 9.4 Device Functional Modes
      1. 9.4.1 Off
      2. 9.4.2 Diagnostic
      3. 9.4.3 Active
      4. 9.4.4 Fault
  11. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 IEC 61000-4-5 Surge
      2. 10.1.2 Inverse Current
      3. 10.1.3 Loss of GND
      4. 10.1.4 Paralleling Channels
      5. 10.1.5 Thermal Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 RILIM Calculation
        2. 10.2.2.2 Diagnostics
          1. 10.2.2.2.1 Selecting the RISNS Value
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.3.4.2 Fault Indication

The following faults are registered on the FLTx pin:

  • FET thermal shutdown
  • Active current regulation
  • Thermal Shutdown caused by current limitation
  • Open-load (FET OFF state only)

Open-load or short-to-supply are not indicated while the switch is enabled, although in on-state these conditions can still be detected through the sensed current (ISNS current). Hence, if there is a fault indication while the channel is enabled, then it must be either due to an overcurrent or overtemperature event. On the other hand, a fault indication while the output (FET) is disabled must be either due to an open load or output short-to-supply.

In versions A, B, C of the device, the open drain FLT pin output is a global fault output. FLT pin indicates a fault when one occurs in either channel. The FLT signal can be deactivated by toggling the EN input of the faulted channel and sequential toggling of ENx inputs can be used to determine the faulted channel. In versions A, B, C of the device the SNS pin also indicates the fault status of the channel, provided the faulted channel is selected with the SEL pin.

In version D of the device, there are two (FLT1 and FLT2) pin outputs corresponding the presence of a fault in each channel. The independent FLTx signals can be used to easily determine the faulted channel. The FLTx signal is deactivated by toggling the EN input of the faulted channel. In version D of the device the SNS pin does not indicate the fault status of the channel, just the load current sense.

Table 9-4 shows the states for both the SNS pin and the FLT pins based on the fault states and ENx/SEL pin state (applies to versions A, B, C). By looking at these pins, it is possible to detect where the fault has occurred. The method to identify the channel that caused the FLT signal is as follows when an MCU is monitoring the SNS pin output. If the SNS is signaling a fault (with ISNSFH current output) while SEL=LO, then the fault is in channel 1, whereas with SEL=HI, the fault is in channel 2. If SNS pin signals fault with SEL at either LO or HI, then both channels are faulted. As discussed earlier, the type of faults (whether it is overcurrent, overtemperature or open-load) can be determined by the state of EN input in each channel. If the SNS pin output is not monitored, it is still possible to identify the channel that is faulted. To do this, the EN pin in each channel must be toggled (LO to HI or HI to LO as the case can be). If the fault indication on the FLT pin is removed by toggling the EN input in a channel, then the fault is in that channel. If the fault indication does not go away with toggling EN input of both channels, then the fault is in both. The time duration for toggling the EN input must be kept below 10 us to ensure that there is no impact on the actual output of the channels.

Table 9-4 Device Fault Mux (Versions A, B, C)
INPUTSOUTPUTS
SELCH1 FAULTCH2 FAULTSNSFLT
000CH1 load currentHigh
001CH1 load currentLow
010Corresponds to fault case(1)Low
011Corresponds to fault case(1)Low
100CH2 load currentHigh
101Corresponds to fault case(1)Low
110CH2 load currentLow
111Corresponds to fault case(1)Low
(1) Table 9-5 describes this behavior

While typically the SNS pin output corresponds to ILOAD, in a fault case the switch turns off and ILOAD goes to zero so the SNS behavior is modified in a fault case. In the event of a fault cases where SEL is monitoring the proper channel, the SNS pin outputs a voltage level corresponding to the fault type to enable improved diagnosis as shown in Table 9-5.

By looking at the combination of the ENx condition, FLT , and SNS pins, it is possible to distinguish between fault states. Each channel has independent fault states, so the table below applies to CH1 when SEL = LO and CH2 when SEL = HI.

Table 9-5 Distinguishing Different Fault Cases (Versions A, B, C)
Channel StateFault CaseSNSFLT
EnabledRegulating current past the initial inrush delay set by ILIMD resistorISNSFHLow
Short-to-supply/open-load0High
TJ overtemperatureISNSFHLow
DisabledShort-to-supply/open-loadISNSFHLow
TJ overtemperature0High

In version D of the device the fault table is shown in Table 9-6. By looking at these pins, it is possible to detect which channel the fault has occurred. As discussed earlier, the type of faults (whether it is overcurrent, overtemperature or open_load) can be determined by the state of EN input in each channel.

Table 9-6 Device Fault Mux (Version D)
INPUTSOUTPUTS
CH1 FAULTCH2 FAULTFLT1FLT2
00HighHigh
01HighLow
10

Low

High
11

Low

Low