SLVSF24C december 2020 – may 2023 TPS272C45
PRODUCTION DATA
To achieve optimal thermal performance, connect the exposed pad to a large copper pour. On the top PCB layer, the pour can extend beyond the package dimensions as shown in the example below. In addition to this, TI recommends to also have a GND plane either on one of the internal PCB layers or on the bottom layer.
Vias must connect this plane to the top GND pour.
Ensure that all external components are placed close to the pins. Device current limiting performance can be harmed if the RILIM is far from the pins and extra parasitics are introduced.