SLUSAR9D December 2011 – December 2021 TPS28225-Q1
PRODUCTION DATA
PIN | TYPE | DESCRIPTION | ||
---|---|---|---|---|
NAME | NO. | |||
SOIC-8 | VSON-8 | |||
BOOT | 2 | 2 | I | Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. |
EN/PG | 7 | 7 | I | Enable and Power Good input-output pin with 1-MΩ impedance. Connect
this pin HIGH to enable and LOW to disable the device. When
disabled, the device draws less than 350-μA bias current. If the VDD voltage is below the UVLO threshold or overtemperature shutdown occurs, this pin is internally pulled low. |
GND | 4 | 4 | GND | Ground pin. All signals are referenced to this node. |
LGATE | 5 | 5 | I | Lower gate-drive sink and source output. Connect to the gate of the low-side power N-Channel MOSFET. |
PHASE | 8 | 8 | I | Connect this pin to the source of the upper MOSFET and the drain of the lower MOSFET. This pin provides a return path for the upper gate driver. |
PWM | 3 | 3 | — | The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, see the Section 7.3.4 section for more details. Connect this pin to the PWM output of the controller. |
UGATE | 1 | 1 | I/O | Upper gate-drive sink and source output. Connect to gate of high-side power N-Channel MOSFET. |
VDD | 6 | 6 | PWR | Connect this pin to a 5-V bias supply. Place a high quality bypass capacitor from this pin to GND. |
Thermal pad | Exposed die pad | O | Connect directly to GND for better thermal performance and EMI. |