SLUSAR9D December 2011 – December 2021 TPS28225-Q1
PRODUCTION DATA
The TPS28225-Q1 device incorporates an undervoltage lockout circuit that keeps the driver disabled and external power FETs in an OFF state when the input supply voltage VDD is insufficient to drive external power FETs reliably. During power up, both gate drive outputs remain low until voltage VDD reaches UVLO threshold, typically 3.5 V. When the UVLO threshold is reached, the condition of gate drive outputs is defined by the input PWM and EN/PG signals. During power down the UVLO threshold is set lower, typically 3 V. The 0.5-V hysteresis is selected to prevent the driver from turning ON and OFF while the input voltage crosses UVLO thresholds, especially with low slew rate. The TPS28225-Q1 has the ability to send a signal back to the system controller that the input supply voltage VDD is insufficient by internally pulling down the EN/PG pin. The TPS28225-Q1 releases EN/PG pin immediately after the VDD has risen above the UVLO threshold.