SLUS791A July   2007  – September 2015 TPS28226

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Undervoltage Lockout (UVLO)
      2. 7.3.2 Output Active Low
      3. 7.3.3 Enable/Power Good
      4. 7.3.4 3-State Input
        1. 7.3.4.1 TPS28226 3-State Exit Mode
        2. 7.3.4.2 External Resistor Interference
      5. 7.3.5 Bootstrap Diode
      6. 7.3.6 Upper and Lower Gate Drivers
      7. 7.3.7 Dead-Time Control
      8. 7.3.8 Thermal Shutdown
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Four Phases Driven by TPS28226 Driver
        2. 8.2.2.2 Switching The MOSFETs
        3. 8.2.2.3 List of Materials
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

To improve the switching characteristics and efficiency of a design, the following layout rules need to be followed.

  • Locate the driver as close as possible to the MOSFETs.
  • Locate the VDD and bootstrap capacitors as close as possible to the driver.
  • Pay special attention to the GND trace. Use the thermal pad of the DFN-8 package as the GND by connecting it to the GND pin. The GND trace or pad from the driver goes directly to the source of the MOSFET but should not include the high current path of the main current flowing through the drain and source of the MOSFET.
  • Use a similar rule for the PHASE node as for the GND.
  • Use wide traces for UGATE and LGATE closely following the related PHASE and GND traces. Eighty to 100 mils width is preferable where possible.
  • Use at least 2 or more vias if the MOSFET driving trace needs to be routed from one layer to another. For the GND the number of vias are determined not only by the parasitic inductance but also by the requirements for the thermal pad.
  • Avoid PWM and enable traces going close to the PHASE node and pad where high dV/dT voltage can induce significant noise into the relatively high impedance leads.

It should be taken into account that poor layout can cause 3% to 5% less efficiency versus a good layout design and can even decrease the reliability of the whole system.

The schematic of one of the phases in a multi-phase synchronous buck regulator and the related layout are shown in Figure 25 and Figure 41. These help to illustrate good design practices. The power stage includes one high-side MOSFET Q10 and two low-side MOSFETS (Q8 and Q9). The driver (U7) is located on bottom side of PCB close to the power MOSFETs. The related switching waveforms during turning ON and OFF of upper FET are shown in Figure 39 and Figure 40. The dead time during turning ON is only 10 ns (Figure 39) and 22 ns during turning OFF (Figure 40).

TPS28226 fig27_lus710.gif Figure 39. Phase Rising-Edge Switching Waveforms (20 ns/div) of the Power Stage in Figure 25
TPS28226 fig28_lus710.gif Figure 40. Phase Falling-Edge Switching Waveforms (10 ns/div) of the Power State in Figure 25

10.2 Layout Example

TPS28226 fig26_lus710.gif Figure 41. Component Placement Based on Schematic in Figure 25