SLVSD74D December   2015  – December 2019 TPS2H160-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Schematic
      2.      Driving a Capacitive Load With Adjustable Current Limit
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Pin Current and Voltage Conventions
      2. 8.3.2 Accurate Current Sense
      3. 8.3.3 Adjustable Current Limit
      4. 8.3.4 Inductive-Load Switching-Off Clamp
      5. 8.3.5 Fault Detection and Reporting
        1. 8.3.5.1 Diagnostic Enable Function
        2. 8.3.5.2 Multiplexing of Current Sense
        3. 8.3.5.3 Fault Table
        4. 8.3.5.4 STx and FAULT Reporting
      6. 8.3.6 Full Diagnostics
        1. 8.3.6.1 Short-to-GND and Overload Detection
        2. 8.3.6.2 Open-Load Detection
          1. 8.3.6.2.1 Channel On
          2. 8.3.6.2.2 Channel Off
        3. 8.3.6.3 Short-to-Battery Detection
        4. 8.3.6.4 Reverse Polarity Detection
        5. 8.3.6.5 Thermal Fault Detection
          1. 8.3.6.5.1 Thermal Shutdown
      7. 8.3.7 Full Protections
        1. 8.3.7.1 UVLO Protection
        2. 8.3.7.2 Loss-of-GND Protection
        3. 8.3.7.3 Protection for Loss of Power Supply
        4. 8.3.7.4 Reverse-Current Protection
        5. 8.3.7.5 MCU I/O Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Working Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
      1. 11.2.1 Without a GND Network
      2. 11.2.2 With a GND Network
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

5 V < VVS < 40 V; −40°C < TJ < 150°C, unless otherwise specified)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OPERATING VOLTAGE
VVS(nom) Nominal operating voltage 4 40 V
VVS(uvr) Undervoltage turnon VVS rises up 3.5 3.7 4 V
VVS(uvf) Undervoltage shutdown VVS falls down 3 3.2 3.4 V
V(uv,hys) Undervoltage shutdown, hysteresis 0.5 V
OPERATING CURRENT
I(op) Nominal operating current(1) VVS = 13.5 V, VINx = 5 V, VDIAG_EN = 0 V, IOUTx = 0.5 A, current limit = 2 A, all channels on 7 mA
I(off) Standby current VVS = 13.5 V, VINx = VDIAG_EN = VCS = VCL = VOUTx = THER = 0 V,
TJ = 25°C		 0.5 µA
VVS = 13.5 V, VINx = VDIAG_EN = VCS = VCL = VOUTx = THER = 0 V,
TJ = 125°C		 5
I(off,diag) Standby current with diagnostic enabled VVS = 13.5 V, VINx = 0 V, VDIAG_EN = 5 V, VVS – VOUTx > V(ol,off), not in open-load mode 6 mA
t(off,diag) Standby mode deglitch time(1) IN from high to low, if deglitch time > t(off,deg), the device enters into standby mode. 10 12.5 15 ms
Ilkg(out) Output leakage current in off-state VVS = 13.5 V, VINx = VDIAG_EN = VOUTx = 0 0.5 µA
POWER STAGE
rDS(on) On-state resistance(1) VVS ≥ 3.5 V, TJ = 25°C 155 mΩ
VVS ≥ 3.5 V, TJ = 150°C 280
ICL(int) Internal current limit Internal current limit value, CL pin connected to GND 9 15 A
ICL(TSD) Current limit during thermal shutdown(1) Internal current limit value under thermal shutdown 6.8 A
External current limit value under thermal shutdown. The percentage of the external current limit setting value 60%
VDS(clamp) Drain-to-source internal clamp voltage 45 65 V
OUTPUT DIODE CHARACTERISTICS
VF Drain−source diode voltage IN = 0, IOUTx = −0.15 A. 0.3 0.7 0.9 V
IR(1), IR(2) Continuous reverse current from source to drain(1) t < 60 s, VINx = 0 V, TJ = 25°C, single channel reversed, short-to-battery condition 2.5 A
t < 60 s, VINx = 0 V, GND pin 1-kΩ resistor in parallel with diode. TJ = 25°C. Reverse-polarity condition, all channels reversed 2
LOGIC INPUT (INx, DIAG_EN, SEL, THER)
VIH Logic high-level voltage 2 V
VIL Logic low-level voltage 0.8 V
R(logic,pd) Logic-pin pulldown resistor INx, SEL, THER, VINx = VSEL = VTHER = 5 V 100 175 230 kΩ
DIAG_EN. VVS = VDIAG_EN = 5 V 150 275 350
DIAGNOSTICS
Ilkg(GND_loss) Output leakage current under GND loss condition 100 µA
V(ol,off) Open-load detection threshold IN = 0 V, when VVS – VOUTx < V(ol,off), duration longer than t(ol,off), then open load is detected, off state 1.6 2.6 V
td(ol,off) Open-load detection threshold deglitch time (see Figure 3) IN = 0 V, when VVS – VOUTx < V(ol,off) , duration longer than t(ol,off), then open load is detected, off state 400 600 800 µs
I(ol,off) Off-state output sink current VINx = 0 V, VDIAG_EN = 5 V, VVS = VOUTx = 13.5 V, TJ = 125°C, open load –75 µA
VOL(STx) Status low-output voltage ISTx = 2 mA, version A only 0.2 V
VOL(FAULT) Fault low-output voltage IFAULT = 2 mA, version B only 0.2 V
tCL(deg) Deglitch time when current limit occurs(1) VINx = VDIAG_EN = 5 V, the deglitch time from current limit toggling to FAULT, STx, CS report. 80 180 µs
T(SD) Thermal shutdown threshold(1) 160 175 °C
T(SD,rst) Thermal shutdown status reset threshold(1) 155 °C
T(SW) Thermal swing shutdown threshold(1) 60 °C
T(hys) Hysteresis for resetting the thermal shutdown or thermal swing(1) 10 °C
CURRENT SENSE (Version B) AND CURRENT LIMIT
K(CS) Current-sense ratio 290
K(CL) Current-limit ratio 2500
VCL(th) Current limit internal threshold(1) 0.8 V
dK(CS) / K(CS) Current-sense accuracy, (ICS × K(CS) – IOUTx) /IOUTx × 100 VVS = 13.5 V, IOUTx ≥ 5 mA –85% 85%
VVS = 13.5 V, IOUTx ≥ 25 mA –17% 17%
VVS = 13.5 V, IOUTx ≥ 50 mA –8% 8%
VVS = 13.5 V, IOUTx ≥ 100 mA –4% 4%
VVS = 13.5 V, IOUTx ≥ 0.5 A –3% 3%
dK(CL) / K(CL) External current limit accuracy(2), (IOUTx – ICL × K(CL)) × 100 / (ICL × K(CL)) VVS = 13.5 V, I(limit) ≥ 0.25 A –20% 20%
VVS = 13.5 V, 0.5 A ≤ I(limit) ≤ 7 A –15% 15%
VCS(lin) Current-sense voltage linear range(1) VVS ≥ 6.5 V 0 4 V
5 V ≤ VVS < 6.5 V 0 VVS – 2.5
IOUTx(lin) Output-current linear range(1) VVS ≥ 6.5 V, VCS(lin) ≤ 4 V 0 2.5 A
5 V ≤ VVS < 6.5 V, VCS(lin) ≤ VVS – 2.5 V 0 2.5
VCS(H) Current sense pin output voltage(1) VVS ≥ 7 V, fault mode 4.5 6.5 V
5 V ≤ VVS < 7 V, fault mode Min(VVS – 2, 4.5) 6.5 V
ICS(H) Current-sense pin output current VCS = 4.5 V, VVS = 13.5 V 15 mA
Ilkg(CS) Current-sense leakage current in disabled mode VDIAG_EN = 0 V, TJ =125ºC 0.5 µA
(1) Value specified by design, not subject to production test
(2) External current limit accuracy is only applicable to overload conditions greater than 1.5 × the current limit setting