SLVSD74D December   2015  – December 2019 TPS2H160-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Schematic
      2.      Driving a Capacitive Load With Adjustable Current Limit
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Pin Current and Voltage Conventions
      2. 8.3.2 Accurate Current Sense
      3. 8.3.3 Adjustable Current Limit
      4. 8.3.4 Inductive-Load Switching-Off Clamp
      5. 8.3.5 Fault Detection and Reporting
        1. 8.3.5.1 Diagnostic Enable Function
        2. 8.3.5.2 Multiplexing of Current Sense
        3. 8.3.5.3 Fault Table
        4. 8.3.5.4 STx and FAULT Reporting
      6. 8.3.6 Full Diagnostics
        1. 8.3.6.1 Short-to-GND and Overload Detection
        2. 8.3.6.2 Open-Load Detection
          1. 8.3.6.2.1 Channel On
          2. 8.3.6.2.2 Channel Off
        3. 8.3.6.3 Short-to-Battery Detection
        4. 8.3.6.4 Reverse Polarity Detection
        5. 8.3.6.5 Thermal Fault Detection
          1. 8.3.6.5.1 Thermal Shutdown
      7. 8.3.7 Full Protections
        1. 8.3.7.1 UVLO Protection
        2. 8.3.7.2 Loss-of-GND Protection
        3. 8.3.7.3 Protection for Loss of Power Supply
        4. 8.3.7.4 Reverse-Current Protection
        5. 8.3.7.5 MCU I/O Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Working Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
      1. 11.2.1 Without a GND Network
      2. 11.2.2 With a GND Network
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Switching Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
td(on) Delay time, VOUTx 10% after VINx↑ (See Figure 1.) VVS = 13.5 V, VDIAG_EN = 5 V, IOUTx = 0.5 A, IN rising edge to 10% of VOUTx 20 50 90 µs
td(off) Delay time, VOUTx 90% after VINx↓ (See Figure 1.) VVS = 13.5 V, VDIAG_EN = 5 V, IOUTx = 0.5 A, IN falling edge to 90% of VOUTx 20 50 90 µs
dV/dt(on) Turnon slew rate VVS = 13.5 V, VDIAG_EN = 5 V, IOUTx = 0.5 A, VOUTx from 10% to 90% 0.1 0.3 0.55 V/µs
dV/dt(off) Turnoff slew rate VVS = 13.5 V, VDIAG_EN = 5 V, IOUTx = 0.5 A, VOUTx from 90% to 10% 0.1 0.35 0.55 V/µs
td(match) td(rise) – td(fall) (See Figure 1.) VVS = 13.5 V, IL = 0.5A. td, rise is the IN rising edge to VOUTx = 90%.
td(fall) is the IN falling edge to VOUTx = 10%.		 –50 50 µs
CURRENT-SENSE CHARACTERISTICS (See Figure 2.)
tCS(off1) CS settling time from DIAG_EN disabled(1) VVS = 13.5 V, VINx = 5 V, IOUTx = 0.5 A. current limit = 2 A. DIAG_EN falling edge to 10% of VCS. 20 µs
tCS(on1) CS settling time from DIAG_EN enabled(1) VVS = 13.5 V, VINx = 5 V, IOUTx = 0.5 A. current limit is 2 A. DIAG_EN rising edge to 90% of VCS. 20 µs
tCS(off2) CS settling time from IN falling edge VVS = 13.5 V, VDIAG_EN = 5 V, IOUTx = 0.5 A. current limit = 2 A. IN falling edge to 10% of VCS 20 100 µs
tCS(on2) CS settling time from IN rising edge VVS = 13.5 V, VDIAG_EN = 5 V, IOUTx = 0.5 A. current limit = 2 A. IN rising edge to 90% of VCS 50 150 µs
tSEL Multi-sense transition delay from channel to channel VDIAG_EN = 5 V, current sense output delay when multi-sense pin SEL transitions from channel to channel 50 µs
(1) Value specified by design, not subject to production test
TPS2H160-Q1 out-dly_SLVSCV8.gifFigure 1. Output Delay Characteristics
TPS2H160-Q1 CS-dly_SLVSCV8.gifFigure 2. CS Delay Characteristics
TPS2H160-Q1 OL-blnk-time_SLVSCV8.gifFigure 3. Open-Load Blanking-Time Characteristics
TPS2H160-Q1 multisens_SLVSD74.gifFigure 4. Multi-Sense Transition Delay