SLVSDZ5A February 2018 – January 2020 TPS2HB50-Q1
PRODUCTION DATA.
To achieve optimal thermal performance, connect the exposed pad to a large copper pour. On the top PCB layer, the pour may extend beyond the package dimensions as shown in the example below. In addition to this, it is recommended to have a VBB plane either on one of the internal PCB layers or on the bottom layer.
Vias should connect this plane to the top VBB pour.
Ensure that all external components are placed close to the pins. Device current limiting performance can be harmed if the RILIM is far from the pins and extra parasitics are introduced.