SLVS227G August   1999  – June 2024

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings for TPS3123
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Dissipation Rating Table
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Manual Reset ( MR)
      2. 7.3.2 Active-High or Active-Low Output
      3. 7.3.3 Push-Pull or Open-Drain Output
      4. 7.3.4 Watchdog Timer (WDI)
    4. 7.4 Device Functional Modes
  9. Device and Documentation Support
    1. 8.1 Device and Documentation Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DBV|5
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Overview

The TPS312x family of supervisors provide circuit initialization and timing supervision. Optional configurations include devices with active-high and active-low output signals (TPS3124/3125/3126), devices with a watchdog timer (TPS3123/3124/3128), and devices with manual reset (MR) pins (TPS3123/3125/3126/3128). RESET output is valid when the supply voltage, VDD, is above 0.75V. For devices with active-low output logic, the device monitors VDD and keeps RESET low as long as VDD remains below the negative threshold voltage, VIT−. For devices with active-high output logic, RESET remains high as long as VDD remains below VIT−. An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time, td, starts after VDD rises above the positive threshold voltage (VIT− + VHYS). When the supply voltage drops below
VIT−, the output becomes active (low) again. All the devices of this family have a fixed-sense threshold voltage,
VIT–, set by an internal voltage divider, so no external components are required.

The TPS312x family is designed to monitor voltages listed on Table 8-2. For devices with the manual reset functionality, a low level at MR causes RESET to become active. For devices with the watch dog timer functionality, when the supervising system fails to retrigger the watchdog circuit within the time-out interval ttout = 0.8 s, RESET output becomes active for the time period (td). This event also reinitializes the watchdog timer. The devices are available in a 5-pin SOT-23 package and are characterized for operation over a temperature range of −40°C to 85°C.