SNVSCF7A December   2022  – August 2024 TPS3435

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics
    9. 6.9  Timing Diagrams
    10. 6.10 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Timeout Watchdog Timer
        1. 7.3.1.1 tWD Timer
        2. 7.3.1.2 Watchdog Enable Disable Operation
        3. 7.3.1.3 tSD Watchdog Start Up Delay
        4. 7.3.1.4 SET Pin Behavior
      2. 7.3.2 Manual RESET
      3. 7.3.3 WDO Output
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Output Assert Delay
        1. 8.1.1.1 Factory-Programmed Output Assert Delay Timing
        2. 8.1.1.2 Adjustable Capacitor Timing
      2. 8.1.2 Watchdog Timer Functionality
        1. 8.1.2.1 Factory-Programmed Timing Options
        2. 8.1.2.2 Adjustable Capacitor Timing
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1: Monitoring a Standard Microcontroller for Timeouts
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Setting the Watchdog Timeout Period
          2. 8.2.1.2.2 Setting Output Assert Delay
          3. 8.2.1.2.3 Setting the Startup Delay
          4. 8.2.1.2.4 Calculating the WDO Pullup Resistor
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

TPS3435 Pin Configuration Option ADDF Package, 8-Pin SOT-23,TPS3435 Top ViewFigure 5-1 Pin Configuration Option A
DDF Package, 8-Pin SOT-23,
TPS3435 Top View
TPS3435 Pin Configuration Option CDDF Package, 8-Pin SOT-23,TPS3435 Top ViewFigure 5-3 Pin Configuration Option C
DDF Package, 8-Pin SOT-23,
TPS3435 Top View
TPS3435 Pin Configuration Option KDSE Package, 6-Pin WSON,TPS3435 Top ViewFigure 5-5 Pin Configuration Option K
DSE Package, 6-Pin WSON,
TPS3435 Top View
TPS3435 Pin Configuration Option BDDF Package, 8-Pin SOT-23,TPS3435 Top ViewFigure 5-2 Pin Configuration Option B
DDF Package, 8-Pin SOT-23,
TPS3435 Top View
TPS3435 Pin Configuration Option JDSE Package, 6-Pin WSON,TPS3435 Top ViewFigure 5-4 Pin Configuration Option J
DSE Package, 6-Pin WSON,
TPS3435 Top View
Table 5-1 Pin Functions
PIN NAME PIN NUMBER I/O DESCRIPTION
PINOUT A PINOUT B PINOUT C PINOUT J PINOUT K
CRST 3 3 — — 2 I Programmable WDO assert time pin. Connect a capacitor between this pin and GND to program the WDO assert time period. See Section 7.3.3 for more details.
CWD 2 2 — — 1 I Programmable watchdog timeout input. Watchdog timeout is set by connecting a capacitor between this pin and ground. See Section 7.3.1.1 for more details.
GND 4 4 4 4 4 — Ground pin
MR 1 — 2 — — I Manual reset pin. A logic low on this pin asserts the WDO output. See Section 7.3.2 for more details.
WDO 7 7 7 5 5 O Watchdog output. Connect WDO to VDD using pull up resistance when using open drain output. WDO is asserted when a watchdog error occurs or MR pin is driven LOW. See Section 7.3.3 for more details.
SET0 5 1 1 1 — I Logic input. SET0, SET1, and WD-EN pins select the watchdog timer scaling and enable-disable the watchdog; see Section 7.3.1.4 for more details.
SET1 — 5 5 — — I Logic input. SET0, SET1, and WD-EN pins select the watchdog timer scaling and enable-disable the watchdog; see Section 7.3.1.4 for more details.
VDD 8 8 8 6 6 I Supply voltage pin. For noisy systems, connecting a 0.1µF bypass capacitor is recommended.
WD-EN — — 6 2 — I Logic input. Logic high input enables the watchdog monitoring feature. See Section 7.3.1.2 for more details.
WDI 6 6 3 3 3 I Watchdog input. A falling transition (edge) must occur at this pin before the timeout expires in order for WDO to not assert. See Section 7.3.1 for more details.