SLVSGF1A
october 2022 – june 2023
TPS3436-Q1
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Revision History
5
Device Comparison
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Timing Requirements
7.7
Switching Characteristics
7.8
Timing Diagrams
7.9
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagrams
8.3
Feature Description
8.3.1
Window Watchdog Timer
8.3.1.1
tWC (Close Window) Timer
8.3.1.2
tWO (Open Window) Timer
8.3.1.3
Watchdog Enable Disable Operation
8.3.1.4
tSD Watchdog Start Up Delay
8.3.1.5
SET Pin Behavior
8.3.2
Manual RESET
8.3.3
WDO Output
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.1.1
Output Assert Delay
9.1.1.1
Factory-Programmed Output Assert Delay Timing
9.1.1.2
Adjustable Capacitor Timing
9.1.2
Watchdog Window Functionality
9.1.2.1
Factory-Programmed Timing Options
9.1.2.2
Adjustable Capacitor Timing
9.2
Typical Applications
9.2.1
Design 1: Monitoring a Microcontroller Watchdog During Operational and Sleep Modes
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.2.1
Determining Window Timings During Operation and Sleep Modes
9.2.1.2.2
Meeting the Output Assert Delay
9.2.1.2.3
Calculating the WDO Pullup Resistor
9.3
Power Supply Recommendations
9.4
Layout
9.4.1
Layout Guidelines
9.4.2
Layout Example
10
Device and Documentation Support
10.1
Receiving Notification of Documentation Updates
10.2
Support Resources
10.3
Trademarks
10.4
Electrostatic Discharge Caution
10.5
Glossary
11
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DDF|8
MPDS569D
Thermal pad, mechanical data (Package|Pins)
Orderable Information
slvsgf1a_oa
slvsgf1a_pm
7.8
Timing Diagrams
Figure 7-1
Functional Timing Diagram