SLVSGF1A october   2022  – june 2023 TPS3436-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Timing Diagrams
    9. 7.9 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Window Watchdog Timer
        1. 8.3.1.1 tWC (Close Window) Timer
        2. 8.3.1.2 tWO (Open Window) Timer
        3. 8.3.1.3 Watchdog Enable Disable Operation
        4. 8.3.1.4 tSD Watchdog Start Up Delay
        5. 8.3.1.5 SET Pin Behavior
      2. 8.3.2 Manual RESET
      3. 8.3.3 WDO Output
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Output Assert Delay
        1. 9.1.1.1 Factory-Programmed Output Assert Delay Timing
        2. 9.1.1.2 Adjustable Capacitor Timing
      2. 9.1.2 Watchdog Window Functionality
        1. 9.1.2.1 Factory-Programmed Timing Options
        2. 9.1.2.2 Adjustable Capacitor Timing
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1: Monitoring a Microcontroller Watchdog During Operational and Sleep Modes
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Determining Window Timings During Operation and Sleep Modes
          2. 9.2.1.2.2 Meeting the Output Assert Delay
          3. 9.2.1.2.3 Calculating the WDO Pullup Resistor
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.3 WDO Output

The TPS3436-Q1 device offers WDO output pin. WDO output is asserted when MR pin voltage is lower than 0.3 X VDD or watchdog timer error is detected.

The output will be asserted for tWDO time when any relevant events described above are detected, except for MR event. The time tWDO can be programmed by connecting a capacitor between CRST pin and GND or device will assert tWDO for fixed time duration as selected by orderable part number. Refer Section 5 section for all available options.

Equation 2 describes the relationship between capacitor value and the time tWDO. Ensure the capacitance meets the recommended operating range. Capacitance outside the recommended range can lead to incorrect operation of the device.

Equation 2. tWDO (sec) = 4.95 x 106 x CCRST (F)

TPS3436-Q1 also offers a unique option of latched output. An orderable with latched output will hold the output in asserted state indefinitely until the device is power cycled or the error condition is addressed. If the output is latched due to MR pin low voltage, the output latch will be released when MR pin voltage rises above 0.7 x VDD level. If the output is latched due to watchdog timer error, the output latch will be released when a WDI negative edge is detected or the device is shutdown and powered up again. Figure 8-11 shows timing behavior of the device with latched output configuration.

GUID-20230113-SS0I-VNQW-GFKS-8M2JBDF4MCFD-low.svg Figure 8-11 Output Latch Timing Behavior