SLVSGF1A october   2022  – june 2023 TPS3436-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Timing Diagrams
    9. 7.9 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Window Watchdog Timer
        1. 8.3.1.1 tWC (Close Window) Timer
        2. 8.3.1.2 tWO (Open Window) Timer
        3. 8.3.1.3 Watchdog Enable Disable Operation
        4. 8.3.1.4 tSD Watchdog Start Up Delay
        5. 8.3.1.5 SET Pin Behavior
      2. 8.3.2 Manual RESET
      3. 8.3.3 WDO Output
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Output Assert Delay
        1. 9.1.1.1 Factory-Programmed Output Assert Delay Timing
        2. 9.1.1.2 Adjustable Capacitor Timing
      2. 9.1.2 Watchdog Window Functionality
        1. 9.1.2.1 Factory-Programmed Timing Options
        2. 9.1.2.2 Adjustable Capacitor Timing
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1: Monitoring a Microcontroller Watchdog During Operational and Sleep Modes
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Determining Window Timings During Operation and Sleep Modes
          2. 9.2.1.2.2 Meeting the Output Assert Delay
          3. 9.2.1.2.3 Calculating the WDO Pullup Resistor
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Device Comparison

Figure 5-1 shows the device naming nomenclature of the TPS3436-Q1. For all possible output types, watchdog time options and output assert delay options, see TPS3436-Q1 Precision Programmable Window Watchdog Timer TPS3436-Q1 Automotive Nano IQ Precision Window Watchdog Timer TPS3436-Q1 Automotive Nano IQ Precision Window Watchdog Timer Features Features Applications Applications Description Description Table of Contents Table of Contents Revision History Revision History Device Comparison Device Comparison Pin Configuration and Functions Pin Configuration and Functions Specifications Specifications Absolute Maximum Ratings Absolute Maximum Ratings ESD Ratings ESD Ratings Recommended Operating Conditions Recommended Operating Conditions Thermal Information Thermal Information Electrical Characteristics Electrical Characteristics Timing Requirements Timing Requirements Switching Characteristics Switching Characteristics Timing Diagrams Timing Diagrams Typical Characteristics Typical Characteristics Detailed Description Detailed Description Overview Overview Functional Block Diagrams Functional Block Diagrams Feature Description Feature Description Window Watchdog Timer Window Watchdog Timer tWC (Close Window) Timer tWC (Close Window) Timer tWO (Open Window) Timer tWO (Open Window) Timer Watchdog Enable Disable Operation Watchdog Enable Disable Operation tSD Watchdog Start Up Delay tSD Watchdog Start Up Delay SET Pin Behavior SET Pin Behavior Manual RESET Manual RESET WDO Output WDO Output Device Functional Modes Device Functional Modes Application and Implementation Application and Implementation Application Information Application Information Output Assert Delay Output Assert Delay Factory-Programmed Output Assert Delay Timing Factory-Programmed Output Assert Delay Timing Adjustable Capacitor Timing Adjustable Capacitor Timing Watchdog Window Functionality Watchdog Window Functionality Factory-Programmed Timing Options Factory-Programmed Timing Options Adjustable Capacitor Timing Adjustable Capacitor Timing Typical Applications Typical Applications Design 1: Monitoring a Microcontroller Watchdog During Operational and Sleep Modes Design 1: Monitoring a Microcontroller Watchdog During Operational and Sleep Modes Design Requirements Design Requirements Detailed Design Procedure Detailed Design Procedure Determining Window Timings During Operation and Sleep Modes Determining Window Timings During Operation and Sleep Modes Meeting the Output Assert Delay Meeting the Output Assert Delay Calculating the WDO Pullup Resistor Calculating the WDO Pullup Resistor Power Supply Recommendations Power Supply Recommendations Layout Layout Layout Guidelines Layout Guidelines Layout Example Layout Example Device and Documentation Support Device and Documentation Support Receiving Notification of Documentation Updates Receiving Notification of Documentation Updates Support Resources Support Resources Trademarks Trademarks Electrostatic Discharge Caution Electrostatic Discharge Caution Glossary Glossary Mechanical, Packaging, and Orderable Information Mechanical, Packaging, and Orderable Information IMPORTANT NOTICE AND DISCLAIMER IMPORTANT NOTICE AND DISCLAIMER TPS3436-Q1 Automotive Nano IQ Precision Window Watchdog Timer TPS3436-Q1 Automotive Nano IQ Precision Window Watchdog TimerTPS3436-Q1Automotive Window Features A 20221210 Advance Information to Production Data release yes AEC-Q100 qualified with the following results: Device temperature grade 1: –40°C to 125°C ambient operating temperature range Factory programmed or user-programmable watchdog timeout ±10% Accurate timer (maximum) Factory programmed close window: 1msec to 100 sec Factory programmed or user-programmable reset delay ±10% Accurate timer (maximum) Factory programmed option: 2 msec to 10 sec Input voltage range: VDD = 1.04 V to 6.0 V Ultra low supply current: IDD = 250 nA (typical) Open-drain, push-pull; active-low outputs Various programmability options: Watchdog enable-disable Watchdog startup delay: no delay to 10 sec Open window to close window ratio option: 1X to 511X Latched output option MR functionality support Features A 20221210 Advance Information to Production Data release yes A 20221210 Advance Information to Production Data release yes A 20221210 Advance Information to Production Data release yes A20221210Advance Information to Production Data releaseyes AEC-Q100 qualified with the following results: Device temperature grade 1: –40°C to 125°C ambient operating temperature range Factory programmed or user-programmable watchdog timeout ±10% Accurate timer (maximum) Factory programmed close window: 1msec to 100 sec Factory programmed or user-programmable reset delay ±10% Accurate timer (maximum) Factory programmed option: 2 msec to 10 sec Input voltage range: VDD = 1.04 V to 6.0 V Ultra low supply current: IDD = 250 nA (typical) Open-drain, push-pull; active-low outputs Various programmability options: Watchdog enable-disable Watchdog startup delay: no delay to 10 sec Open window to close window ratio option: 1X to 511X Latched output option MR functionality support AEC-Q100 qualified with the following results: Device temperature grade 1: –40°C to 125°C ambient operating temperature range Factory programmed or user-programmable watchdog timeout ±10% Accurate timer (maximum) Factory programmed close window: 1msec to 100 sec Factory programmed or user-programmable reset delay ±10% Accurate timer (maximum) Factory programmed option: 2 msec to 10 sec Input voltage range: VDD = 1.04 V to 6.0 V Ultra low supply current: IDD = 250 nA (typical) Open-drain, push-pull; active-low outputs Various programmability options: Watchdog enable-disable Watchdog startup delay: no delay to 10 sec Open window to close window ratio option: 1X to 511X Latched output option MR functionality support AEC-Q100 qualified with the following results: Device temperature grade 1: –40°C to 125°C ambient operating temperature range Factory programmed or user-programmable watchdog timeout ±10% Accurate timer (maximum) Factory programmed close window: 1msec to 100 sec Factory programmed or user-programmable reset delay ±10% Accurate timer (maximum) Factory programmed option: 2 msec to 10 sec Input voltage range: VDD = 1.04 V to 6.0 V Ultra low supply current: IDD = 250 nA (typical) Open-drain, push-pull; active-low outputs Various programmability options: Watchdog enable-disable Watchdog startup delay: no delay to 10 sec Open window to close window ratio option: 1X to 511X Latched output option MR functionality support AEC-Q100 qualified with the following results: Device temperature grade 1: –40°C to 125°C ambient operating temperature range Device temperature grade 1: –40°C to 125°C ambient operating temperature range Device temperature grade 1: –40°C to 125°C ambient operating temperature rangeFactory programmed or user-programmable watchdog timeout ±10% Accurate timer (maximum) Factory programmed close window: 1msec to 100 sec ±10% Accurate timer (maximum) Factory programmed close window: 1msec to 100 sec ±10% Accurate timer (maximum)Factory programmed close window: 1msec to 100 secFactory programmed or user-programmable reset delay ±10% Accurate timer (maximum) Factory programmed option: 2 msec to 10 sec ±10% Accurate timer (maximum) Factory programmed option: 2 msec to 10 sec ±10% Accurate timer (maximum)Factory programmed option: 2 msec to 10 secInput voltage range: VDD = 1.04 V to 6.0 VDDUltra low supply current: IDD = 250 nA (typical)DDOpen-drain, push-pull; active-low outputsVarious programmability options: Watchdog enable-disable Watchdog startup delay: no delay to 10 sec Open window to close window ratio option: 1X to 511X Latched output option Watchdog enable-disable Watchdog startup delay: no delay to 10 sec Open window to close window ratio option: 1X to 511X Latched output option Watchdog enable-disableWatchdog startup delay: no delay to 10 secOpen window to close window ratio option: 1X to 511XLatched output option MR functionality supportMR Applications On-board (OBC) and wireless charger Driver monitoring Battery Management System (BMS) Front camera Surround view system ECU Applications On-board (OBC) and wireless charger Driver monitoring Battery Management System (BMS) Front camera Surround view system ECU On-board (OBC) and wireless charger Driver monitoring Battery Management System (BMS) Front camera Surround view system ECU On-board (OBC) and wireless charger Driver monitoring Battery Management System (BMS) Front camera Surround view system ECU On-board (OBC) and wireless charger On-board (OBC) and wireless charger Driver monitoring Driver monitoring Battery Management System (BMS) Battery Management System (BMS) Front camera Front camera Surround view system ECU Surround view system ECU Description The TPS3436-Q1 is an ultra-low power consumption (250 nA typical) device offering a programmable window watchdog timer. The TPS3436-Q1 offers a high accuracy window watchdog timer with host of features for a wide variety of applications. The close window timer can be factory programmed or user programmed using an external capacitor. The open window to close window ratio can be changed on-the-fly using a combination of logic pins. The watchdog also offers unique features such as enable-disable, start-up delay. The WDO delay can be set by factory-programmed default delay settings or programmed by an external capacitor. The device also offers a latched output operation where the output is latched until the watchdog fault is cleared. The TPS3436-Q1 provides a performance upgrade alternative to TPS3430-Q1 device family. The TPS3436-Q1 is available in a small 8-pin SOT-23 package. Device Information PART NUMBER PACKAGE #GUID-A90FCBEA-9211-41EC-A530-F55740F95637/DEVINFONOTE BODY SIZE (NOM) TPS3436-Q1 DDF (8) 2.90 mm × 1.60 mm For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Circuit Description The TPS3436-Q1 is an ultra-low power consumption (250 nA typical) device offering a programmable window watchdog timer. The TPS3436-Q1 offers a high accuracy window watchdog timer with host of features for a wide variety of applications. The close window timer can be factory programmed or user programmed using an external capacitor. The open window to close window ratio can be changed on-the-fly using a combination of logic pins. The watchdog also offers unique features such as enable-disable, start-up delay. The WDO delay can be set by factory-programmed default delay settings or programmed by an external capacitor. The device also offers a latched output operation where the output is latched until the watchdog fault is cleared. The TPS3436-Q1 provides a performance upgrade alternative to TPS3430-Q1 device family. The TPS3436-Q1 is available in a small 8-pin SOT-23 package. Device Information PART NUMBER PACKAGE #GUID-A90FCBEA-9211-41EC-A530-F55740F95637/DEVINFONOTE BODY SIZE (NOM) TPS3436-Q1 DDF (8) 2.90 mm × 1.60 mm For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Circuit The TPS3436-Q1 is an ultra-low power consumption (250 nA typical) device offering a programmable window watchdog timer. The TPS3436-Q1 offers a high accuracy window watchdog timer with host of features for a wide variety of applications. The close window timer can be factory programmed or user programmed using an external capacitor. The open window to close window ratio can be changed on-the-fly using a combination of logic pins. The watchdog also offers unique features such as enable-disable, start-up delay. The WDO delay can be set by factory-programmed default delay settings or programmed by an external capacitor. The device also offers a latched output operation where the output is latched until the watchdog fault is cleared. The TPS3436-Q1 provides a performance upgrade alternative to TPS3430-Q1 device family. The TPS3436-Q1 is available in a small 8-pin SOT-23 package. Device Information PART NUMBER PACKAGE #GUID-A90FCBEA-9211-41EC-A530-F55740F95637/DEVINFONOTE BODY SIZE (NOM) TPS3436-Q1 DDF (8) 2.90 mm × 1.60 mm For all available packages, see the orderable addendum at the end of the data sheet. The TPS3436-Q1 is an ultra-low power consumption (250 nA typical) device offering a programmable window watchdog timer. TPS3436-Q1window The TPS3436-Q1 offers a high accuracy window watchdog timer with host of features for a wide variety of applications. The close window timer can be factory programmed or user programmed using an external capacitor. The open window to close window ratio can be changed on-the-fly using a combination of logic pins. The watchdog also offers unique features such as enable-disable, start-up delay.TPS3436-Q1The WDO delay can be set by factory-programmed default delay settings or programmed by an external capacitor. The device also offers a latched output operation where the output is latched until the watchdog fault is cleared.WDOThe TPS3436-Q1 provides a performance upgrade alternative to TPS3430-Q1 device family. The TPS3436-Q1 is available in a small 8-pin SOT-23 package.TPS3436-Q1 TPS3430-Q1 TPS3430-Q1TPS3436-Q1 Device Information PART NUMBER PACKAGE #GUID-A90FCBEA-9211-41EC-A530-F55740F95637/DEVINFONOTE BODY SIZE (NOM) TPS3436-Q1 DDF (8) 2.90 mm × 1.60 mm Device Information PART NUMBER PACKAGE #GUID-A90FCBEA-9211-41EC-A530-F55740F95637/DEVINFONOTE BODY SIZE (NOM) TPS3436-Q1 DDF (8) 2.90 mm × 1.60 mm PART NUMBER PACKAGE #GUID-A90FCBEA-9211-41EC-A530-F55740F95637/DEVINFONOTE BODY SIZE (NOM) PART NUMBER PACKAGE #GUID-A90FCBEA-9211-41EC-A530-F55740F95637/DEVINFONOTE BODY SIZE (NOM) PART NUMBERPACKAGE #GUID-A90FCBEA-9211-41EC-A530-F55740F95637/DEVINFONOTE #GUID-A90FCBEA-9211-41EC-A530-F55740F95637/DEVINFONOTE #GUID-A90FCBEA-9211-41EC-A530-F55740F95637/DEVINFONOTEBODY SIZE (NOM) TPS3436-Q1 DDF (8) 2.90 mm × 1.60 mm TPS3436-Q1 DDF (8) 2.90 mm × 1.60 mm TPS3436-Q1 TPS3436-Q1DDF (8)2.90 mm × 1.60 mm For all available packages, see the orderable addendum at the end of the data sheet. For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Circuit Typical Application Circuit Typical Application Circuit Typical Application Circuit Table of Contents yes Table of Contents yes yes yes Revision History yes October 2022 June 2023 * A Revision History yes October 2022 June 2023 * A yes October 2022 June 2023 * A yesOctober 2022June 2023*A Device Comparison shows the device naming nomenclature of the TPS3436-Q1. For all possible output types, watchdog time options and output assert delay options, see for more details. Contact TI sales representatives or on TI's E2E forum for detail and availability of other options. Device Naming Nomenclature TPS3436-Q1 belongs to family of pin compatible devices offering different feature sets as highlighted in . Pin Compatible Device Families DEVICE VOLTAGE SUPERVISOR TYPE OF WATCHDOG TPS35-Q1 Yes Timeout TPS36-Q1 Yes Window TPS3435-Q1 No Timeout TPS3436-Q1 No Window Device Comparison shows the device naming nomenclature of the TPS3436-Q1. For all possible output types, watchdog time options and output assert delay options, see for more details. Contact TI sales representatives or on TI's E2E forum for detail and availability of other options. Device Naming Nomenclature TPS3436-Q1 belongs to family of pin compatible devices offering different feature sets as highlighted in . Pin Compatible Device Families DEVICE VOLTAGE SUPERVISOR TYPE OF WATCHDOG TPS35-Q1 Yes Timeout TPS36-Q1 Yes Window TPS3435-Q1 No Timeout TPS3436-Q1 No Window shows the device naming nomenclature of the TPS3436-Q1. For all possible output types, watchdog time options and output assert delay options, see for more details. Contact TI sales representatives or on TI's E2E forum for detail and availability of other options. Device Naming Nomenclature TPS3436-Q1 belongs to family of pin compatible devices offering different feature sets as highlighted in . Pin Compatible Device Families DEVICE VOLTAGE SUPERVISOR TYPE OF WATCHDOG TPS35-Q1 Yes Timeout TPS36-Q1 Yes Window TPS3435-Q1 No Timeout TPS3436-Q1 No Window shows the device naming nomenclature of the TPS3436-Q1. For all possible output types, watchdog time options and output assert delay options, see for more details. Contact TI sales representatives or on TI's E2E forum for detail and availability of other options.TPS3436-Q1E2E forum Device Naming Nomenclature Device Naming Nomenclature TPS3436-Q1 belongs to family of pin compatible devices offering different feature sets as highlighted in .TPS3436-Q1 Pin Compatible Device Families DEVICE VOLTAGE SUPERVISOR TYPE OF WATCHDOG TPS35-Q1 Yes Timeout TPS36-Q1 Yes Window TPS3435-Q1 No Timeout TPS3436-Q1 No Window Pin Compatible Device Families DEVICE VOLTAGE SUPERVISOR TYPE OF WATCHDOG TPS35-Q1 Yes Timeout TPS36-Q1 Yes Window TPS3435-Q1 No Timeout TPS3436-Q1 No Window DEVICE VOLTAGE SUPERVISOR TYPE OF WATCHDOG DEVICE VOLTAGE SUPERVISOR TYPE OF WATCHDOG DEVICEVOLTAGE SUPERVISORTYPE OF WATCHDOG TPS35-Q1 Yes Timeout TPS36-Q1 Yes Window TPS3435-Q1 No Timeout TPS3436-Q1 No Window TPS35-Q1 Yes Timeout TPS35-Q1 TPS35-Q1 TPS35-Q1YesTimeout TPS36-Q1 Yes Window TPS36-Q1 TPS36-Q1 TPS36-Q1YesWindow TPS3435-Q1 No Timeout TPS3435-Q1 TPS3435-Q1 TPS3435-Q1NoTimeout TPS3436-Q1 No Window TPS3436-Q1 TPS3436-Q1 TPS3436-Q1NoWindow Pin Configuration and Functions Pin Configuration Option A
DDF Package, 8-Pin SOT-23,
TPS3436-Q1 Top View Pin Configuration Option B
DDF Package, 8-Pin SOT-23,
TPS3436-Q1 Top View Pin Configuration Option C
DDF Package, 8-Pin SOT-23,
TPS3436-Q1 Top View Pin Functions PIN NAME PIN NUMBER I/O DESCRIPTION PINOUT A PINOUT B PINOUT C CRST 3 3 — I Programmable WDO assert time pin. Connect a capacitor between this pin and GND to program the WDO assert time period. See for more details. CWD 2 2 — I Programmable watchdog timeout input. Watchdog close time is set by connecting a capacitor between this pin and ground. See for more details. GND 4 4 4 — Ground pin MR 1 — 2 I Manual reset pin. A logic low on this pin asserts the WDO output. See for more details. WDO 7 7 7 O Watchdog output. Connect WDO to VDD using pull up resistance when using open drain output. WDO is asserted when a watchdog error occurs or MR pin is driven LOW. See for more details. SET0 5 1 1 I Logic input. SET0, SET1, and WD-EN pins select the watchdog window ratios and enable-disable the watchdog; see for more details. SET1 — 5 5 I Logic input. SET0, SET1, and WD-EN pins select the watchdog window ratios and enable-disable the watchdog; see for more details. VDD 8 8 8 I Supply voltage pin. For noisy systems, connecting a 0.1-µF bypass capacitor is recommended. WD-EN — — 6 I Logic input. Logic high input enables the watchdog monitoring feature. See for more details. WDI 6 6 3 I Watchdog input. A falling transition (edge) must occur at this pin during the open window in order for WDO to not assert. See for more details. Pin Configuration and Functions Pin Configuration Option A
DDF Package, 8-Pin SOT-23,
TPS3436-Q1 Top View Pin Configuration Option B
DDF Package, 8-Pin SOT-23,
TPS3436-Q1 Top View Pin Configuration Option C
DDF Package, 8-Pin SOT-23,
TPS3436-Q1 Top View Pin Functions PIN NAME PIN NUMBER I/O DESCRIPTION PINOUT A PINOUT B PINOUT C CRST 3 3 — I Programmable WDO assert time pin. Connect a capacitor between this pin and GND to program the WDO assert time period. See for more details. CWD 2 2 — I Programmable watchdog timeout input. Watchdog close time is set by connecting a capacitor between this pin and ground. See for more details. GND 4 4 4 — Ground pin MR 1 — 2 I Manual reset pin. A logic low on this pin asserts the WDO output. See for more details. WDO 7 7 7 O Watchdog output. Connect WDO to VDD using pull up resistance when using open drain output. WDO is asserted when a watchdog error occurs or MR pin is driven LOW. See for more details. SET0 5 1 1 I Logic input. SET0, SET1, and WD-EN pins select the watchdog window ratios and enable-disable the watchdog; see for more details. SET1 — 5 5 I Logic input. SET0, SET1, and WD-EN pins select the watchdog window ratios and enable-disable the watchdog; see for more details. VDD 8 8 8 I Supply voltage pin. For noisy systems, connecting a 0.1-µF bypass capacitor is recommended. WD-EN — — 6 I Logic input. Logic high input enables the watchdog monitoring feature. See for more details. WDI 6 6 3 I Watchdog input. A falling transition (edge) must occur at this pin during the open window in order for WDO to not assert. See for more details. Pin Configuration Option A
DDF Package, 8-Pin SOT-23,
TPS3436-Q1 Top View Pin Configuration Option B
DDF Package, 8-Pin SOT-23,
TPS3436-Q1 Top View Pin Configuration Option C
DDF Package, 8-Pin SOT-23,
TPS3436-Q1 Top View Pin Functions PIN NAME PIN NUMBER I/O DESCRIPTION PINOUT A PINOUT B PINOUT C CRST 3 3 — I Programmable WDO assert time pin. Connect a capacitor between this pin and GND to program the WDO assert time period. See for more details. CWD 2 2 — I Programmable watchdog timeout input. Watchdog close time is set by connecting a capacitor between this pin and ground. See for more details. GND 4 4 4 — Ground pin MR 1 — 2 I Manual reset pin. A logic low on this pin asserts the WDO output. See for more details. WDO 7 7 7 O Watchdog output. Connect WDO to VDD using pull up resistance when using open drain output. WDO is asserted when a watchdog error occurs or MR pin is driven LOW. See for more details. SET0 5 1 1 I Logic input. SET0, SET1, and WD-EN pins select the watchdog window ratios and enable-disable the watchdog; see for more details. SET1 — 5 5 I Logic input. SET0, SET1, and WD-EN pins select the watchdog window ratios and enable-disable the watchdog; see for more details. VDD 8 8 8 I Supply voltage pin. For noisy systems, connecting a 0.1-µF bypass capacitor is recommended. WD-EN — — 6 I Logic input. Logic high input enables the watchdog monitoring feature. See for more details. WDI 6 6 3 I Watchdog input. A falling transition (edge) must occur at this pin during the open window in order for WDO to not assert. See for more details. Pin Configuration Option A
DDF Package, 8-Pin SOT-23,
TPS3436-Q1 Top View Pin Configuration Option B
DDF Package, 8-Pin SOT-23,
TPS3436-Q1 Top View Pin Configuration Option C
DDF Package, 8-Pin SOT-23,
TPS3436-Q1 Top View Pin Configuration Option A
DDF Package, 8-Pin SOT-23,
TPS3436-Q1 Top View Pin Configuration Option A
DDF Package, 8-Pin SOT-23,
TPS3436-Q1 Top View DDF Package, 8-Pin SOT-23, TPS3436-Q1 Top ViewTPS3436-Q1 Pin Configuration Option B
DDF Package, 8-Pin SOT-23,
TPS3436-Q1 Top View Pin Configuration Option B
DDF Package, 8-Pin SOT-23,
TPS3436-Q1 Top View DDF Package, 8-Pin SOT-23, TPS3436-Q1 Top ViewTPS3436-Q1 Pin Configuration Option C
DDF Package, 8-Pin SOT-23,
TPS3436-Q1 Top View Pin Configuration Option C
DDF Package, 8-Pin SOT-23,
TPS3436-Q1 Top View DDF Package, 8-Pin SOT-23, TPS3436-Q1 Top ViewTPS3436-Q1 Pin Functions PIN NAME PIN NUMBER I/O DESCRIPTION PINOUT A PINOUT B PINOUT C CRST 3 3 — I Programmable WDO assert time pin. Connect a capacitor between this pin and GND to program the WDO assert time period. See for more details. CWD 2 2 — I Programmable watchdog timeout input. Watchdog close time is set by connecting a capacitor between this pin and ground. See for more details. GND 4 4 4 — Ground pin MR 1 — 2 I Manual reset pin. A logic low on this pin asserts the WDO output. See for more details. WDO 7 7 7 O Watchdog output. Connect WDO to VDD using pull up resistance when using open drain output. WDO is asserted when a watchdog error occurs or MR pin is driven LOW. See for more details. SET0 5 1 1 I Logic input. SET0, SET1, and WD-EN pins select the watchdog window ratios and enable-disable the watchdog; see for more details. SET1 — 5 5 I Logic input. SET0, SET1, and WD-EN pins select the watchdog window ratios and enable-disable the watchdog; see for more details. VDD 8 8 8 I Supply voltage pin. For noisy systems, connecting a 0.1-µF bypass capacitor is recommended. WD-EN — — 6 I Logic input. Logic high input enables the watchdog monitoring feature. See for more details. WDI 6 6 3 I Watchdog input. A falling transition (edge) must occur at this pin during the open window in order for WDO to not assert. See for more details. Pin Functions PIN NAME PIN NUMBER I/O DESCRIPTION PINOUT A PINOUT B PINOUT C CRST 3 3 — I Programmable WDO assert time pin. Connect a capacitor between this pin and GND to program the WDO assert time period. See for more details. CWD 2 2 — I Programmable watchdog timeout input. Watchdog close time is set by connecting a capacitor between this pin and ground. See for more details. GND 4 4 4 — Ground pin MR 1 — 2 I Manual reset pin. A logic low on this pin asserts the WDO output. See for more details. WDO 7 7 7 O Watchdog output. Connect WDO to VDD using pull up resistance when using open drain output. WDO is asserted when a watchdog error occurs or MR pin is driven LOW. See for more details. SET0 5 1 1 I Logic input. SET0, SET1, and WD-EN pins select the watchdog window ratios and enable-disable the watchdog; see for more details. SET1 — 5 5 I Logic input. SET0, SET1, and WD-EN pins select the watchdog window ratios and enable-disable the watchdog; see for more details. VDD 8 8 8 I Supply voltage pin. For noisy systems, connecting a 0.1-µF bypass capacitor is recommended. WD-EN — — 6 I Logic input. Logic high input enables the watchdog monitoring feature. See for more details. WDI 6 6 3 I Watchdog input. A falling transition (edge) must occur at this pin during the open window in order for WDO to not assert. See for more details. PIN NAME PIN NUMBER I/O DESCRIPTION PINOUT A PINOUT B PINOUT C PIN NAME PIN NUMBER I/O DESCRIPTION PIN NAMEPIN NUMBERI/ODESCRIPTION PINOUT A PINOUT B PINOUT C PINOUT APINOUT BPINOUT C CRST 3 3 — I Programmable WDO assert time pin. Connect a capacitor between this pin and GND to program the WDO assert time period. See for more details. CWD 2 2 — I Programmable watchdog timeout input. Watchdog close time is set by connecting a capacitor between this pin and ground. See for more details. GND 4 4 4 — Ground pin MR 1 — 2 I Manual reset pin. A logic low on this pin asserts the WDO output. See for more details. WDO 7 7 7 O Watchdog output. Connect WDO to VDD using pull up resistance when using open drain output. WDO is asserted when a watchdog error occurs or MR pin is driven LOW. See for more details. SET0 5 1 1 I Logic input. SET0, SET1, and WD-EN pins select the watchdog window ratios and enable-disable the watchdog; see for more details. SET1 — 5 5 I Logic input. SET0, SET1, and WD-EN pins select the watchdog window ratios and enable-disable the watchdog; see for more details. VDD 8 8 8 I Supply voltage pin. For noisy systems, connecting a 0.1-µF bypass capacitor is recommended. WD-EN — — 6 I Logic input. Logic high input enables the watchdog monitoring feature. See for more details. WDI 6 6 3 I Watchdog input. A falling transition (edge) must occur at this pin during the open window in order for WDO to not assert. See for more details. CRST 3 3 — I Programmable WDO assert time pin. Connect a capacitor between this pin and GND to program the WDO assert time period. See for more details. CRST33—IProgrammable WDO assert time pin. Connect a capacitor between this pin and GND to program the WDO assert time period. See for more details. CWD 2 2 — I Programmable watchdog timeout input. Watchdog close time is set by connecting a capacitor between this pin and ground. See for more details. CWD22—IProgrammable watchdog timeout input. Watchdog close time is set by connecting a capacitor between this pin and ground. See for more details.close time GND 4 4 4 — Ground pin GND444—Ground pin MR 1 — 2 I Manual reset pin. A logic low on this pin asserts the WDO output. See for more details. MR MR1—2IManual reset pin. A logic low on this pin asserts the WDO output. See for more details.WDO WDO 7 7 7 O Watchdog output. Connect WDO to VDD using pull up resistance when using open drain output. WDO is asserted when a watchdog error occurs or MR pin is driven LOW. See for more details. WDO WDO777OWatchdog output. Connect WDO to VDD using pull up resistance when using open drain output. WDO is asserted when a watchdog error occurs or MR pin is driven LOW. See for more details.WDOWDOMR SET0 5 1 1 I Logic input. SET0, SET1, and WD-EN pins select the watchdog window ratios and enable-disable the watchdog; see for more details. SET0511ILogic input. SET0, SET1, and WD-EN pins select the watchdog window ratios and enable-disable the watchdog; see for more details.window ratios SET1 — 5 5 I Logic input. SET0, SET1, and WD-EN pins select the watchdog window ratios and enable-disable the watchdog; see for more details. SET1—55ILogic input. SET0, SET1, and WD-EN pins select the watchdog window ratios and enable-disable the watchdog; see for more details.window ratios VDD 8 8 8 I Supply voltage pin. For noisy systems, connecting a 0.1-µF bypass capacitor is recommended. VDD888ISupply voltage pin. For noisy systems, connecting a 0.1-µF bypass capacitor is recommended. WD-EN — — 6 I Logic input. Logic high input enables the watchdog monitoring feature. See for more details. WD-EN——6ILogic input. Logic high input enables the watchdog monitoring feature. See for more details. WDI 6 6 3 I Watchdog input. A falling transition (edge) must occur at this pin during the open window in order for WDO to not assert. See for more details. WDI663IWatchdog input. A falling transition (edge) must occur at this pin during the open window in order for WDO to not assert. See for more details.during the open windowWDO Specifications Absolute Maximum Ratings over operating free-air temperature range, unless otherwise noted#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER1 MIN MAX UNIT Voltage VDD –0.3 6.5 V Voltage CWD, CRST, WD–EN, SETx, WDI,  MR (2), WDO (Push Pull) –0.3 VDD+0.3 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/SF_WMY9TRSL1 V   WDO (Open Drain) –0.3 6.5 Current  WDO pin –20 20 mA Temperature #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER2 Operating ambient temperature, TA –40 125 ℃ Temperature Storage, Tstg –65 150 Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR.  The absolute maximum rating is (VDD + 0.3) V or 6.5 V, whichever is smaller As a result of the low dissipated power in this device, it is assumed that TJ = TA. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244048/A_SUPERVISOR_VVCM_3_ESD_RATINGS_AUTOMOTIVE_FOOTER1 ±2000 V Charged device model (CDM), per AEC Q100-011 ±750 AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Voltage VDD (Active Low output) 0.9 6 V CWD, CRST, WD–EN, SETx, WDI, MR (1) 0 VDD WDO (Open Drain) 0 6 WDO (Push Pull) 0 VDD Current WDO pin current –5 5 mA CRST CRST pin capacitor range 1.5 1800 nF CWD CWD pin capacitor range 1.5 1000 nF TA Operating ambient temperature –40 125 ℃ If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR. VMR should not be higher than VDD. Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244050/A_SUPERVISOR_VVCM_5_THERMAL_FOOTER1 TPS3436-Q1 UNIT DDF (SOT23-8) 8 PINS RθJA Junction-to-ambient thermal resistance 175.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 94.7 °C/W RθJB Junction-to-board thermal resistance 92.4 °C/W ψJT Junction-to-top characterization parameter 8.4 °C/W ψJB Junction-to-board characterization parameter 91.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Electrical Characteristics At 1.04 V ≤ VDD ≤ 6 V, MR = Open, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT COMMON PARAMETERS VDD Input supply voltage Active LOW output 1.04 6 V IDD Supply current into VDD pin #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245017/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER5_SF2_SF1 TA = –40℃ to 85℃  0.25 0.8 µA 0.25 3 VIL Low level input voltage WD–EN, WDI, SETx, MR (3) 0.3VDD V VIH High level input voltage WD–EN, WDI, SETx, MR (3) 0.7VDD V R MR Manual reset internal pull-up resistance 100 kΩ WDO (Open-drain active-low) VOL Low level output voltage  VDD =1.5 VIOUT(Sink) = 500 µA 300 mV VDD = 3.3 VIOUT(Sink) = 2 mA 300 Ilkg(OD) Open-Drain output leakage current VDD = VPULLUP = 6VTA = –40℃ to 85℃ 10 30 nA VDD = VPULLUP = 6V 10 60 nA WDO (Push-pull active-low) VPOR Power on WDO voltage (5) VOH(min) = 0.8 VDDIout (source) = 15 µA 900 mV VOL Low level output voltage  VDD = 1.5 VIOUT(Sink) = 500 µA 300 mV VDD = 3.3 VIOUT(Sink) = 2 mA 300 VOH High level output voltage  VDD = 1.8 VIOUT(Source) = 500 µA 0.8VDD V VDD = 3.3 VIOUT(Source) = 500 µA 0.8VDD VDD = 6 VIOUT(Source) = 2 mA 0.8VDD If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR. VPOR is the minimum VDD voltage level for a controlled output state Timing Requirements At 1.04 V ≤ VDD ≤ 6 V, MR = Open, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output RESET / WDO load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t MR_PW MR pin pulse duration to assert output 100 ns tP-WD WDI pulse duration to start next frame #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245016/SFKSOT305GOW 500 ns tHD-WDEN WD–EN hold time to enable or disable WD operation #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245016/SFKSOT305GOW 200 µs tHD-SETx SETx hold time to change WD timer setting #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245016/SFKSOT305GOW 150 µs tWC Watchdog close window time period Orderable Option TPS3436xxB 0.8 1 1.2 ms Orderable Option TPS3436xxC 4 5 6 Orderable Option TPS3436xxD 9 10 11 Orderable Option TPS3436xxE 18 20 22 Orderable Option TPS3436xxF 45 50 55 Orderable Option TPS3436xxG 90 100 110 Orderable Option TPS3436xxH 180 200 220 Orderable Option TPS3436xxI 0.9 1 1.1 s Orderable Option TPS3436xxJ 1.26 1.4 1.54 Orderable Option TPS3436xxK 1.44 1.6 1.76 Orderable Option TPS3436xxL 9 10 11 Orderable Option TPS3436xxM 45 50 55 Orderable Option TPS3436xxN 90 100 110 tWO Watchdog open window time period SETx pin decide multipler n (n-1) X tWC ms Not production tested Switching Characteristics At 1.04 V ≤ VDD ≤ 6 V, MR = Open, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output RESET / WDO load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tSTRT Startup delay #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245018/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER1_SF1_SF2_SF1 CCRST pin = Open or NC  500 µs tSD Watchdog startup delay Orderable part number TPS3436xA, TPS343xG 0 ms Orderable part number TPS3436xB, TPS3436xH 180 200 220 Orderable part number TPS3436xC, TPS3436xI 450 500 550 Orderable part number TPS3436xD, TPS3436xJ 0.9 1 1.1 s Orderable part number TPS3436xE, TPS3436xK 4.5 5 5.5 Orderable part number TPS3436xF, TPS3436xL 9 10 11 tWDO Watchdog assert time delay Orderable part number TPS3436xxxxB 1.6 2 2.4 ms Orderable part number TPS3436xxxxC 9 10 11 ms Orderable part number TPS3436xxxxD 22.5 25 27.5 ms Orderable part number TPS3436xxxxE 45 50 55 ms Orderable part number TPS3436xxxxF 90 100 110 ms Orderable part number TPS3436xxxxG 180 200 220 ms Orderable part number TPS3436xxxxH 0.9 1 1.1 s Orderable part number TPS3436xxxxI 9 10 11 s t MR_WDO Propagation delay from MR low to WDO assertion VDD ≥ 1.25 V, MR = V MR_H to V MR_L 100 ns Specified by design parameter. Timing Diagrams * Added a footnote to for tINIT no Functional Timing Diagram Typical Characteristics all curves are taken at TA = 25°C (unless otherwise noted) Timer Accuracy vs Temperature Timer Accuracy Histogram tWC vs Capacitance tWDO vs Capacitance WDO VOL vs I sink, VDD = 1.5 V WDO VOL vs I sink, VDD = 3.3 V WDO VOH vs I source, VDD = 2.0 V WDO VOH vs I source, VDD = 6.0 V Supply Current vs Power-Supply Voltage Specifications Absolute Maximum Ratings over operating free-air temperature range, unless otherwise noted#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER1 MIN MAX UNIT Voltage VDD –0.3 6.5 V Voltage CWD, CRST, WD–EN, SETx, WDI,  MR (2), WDO (Push Pull) –0.3 VDD+0.3 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/SF_WMY9TRSL1 V   WDO (Open Drain) –0.3 6.5 Current  WDO pin –20 20 mA Temperature #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER2 Operating ambient temperature, TA –40 125 ℃ Temperature Storage, Tstg –65 150 Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR.  The absolute maximum rating is (VDD + 0.3) V or 6.5 V, whichever is smaller As a result of the low dissipated power in this device, it is assumed that TJ = TA. Absolute Maximum Ratings over operating free-air temperature range, unless otherwise noted#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER1 MIN MAX UNIT Voltage VDD –0.3 6.5 V Voltage CWD, CRST, WD–EN, SETx, WDI,  MR (2), WDO (Push Pull) –0.3 VDD+0.3 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/SF_WMY9TRSL1 V   WDO (Open Drain) –0.3 6.5 Current  WDO pin –20 20 mA Temperature #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER2 Operating ambient temperature, TA –40 125 ℃ Temperature Storage, Tstg –65 150 Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR.  The absolute maximum rating is (VDD + 0.3) V or 6.5 V, whichever is smaller As a result of the low dissipated power in this device, it is assumed that TJ = TA. over operating free-air temperature range, unless otherwise noted#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER1 MIN MAX UNIT Voltage VDD –0.3 6.5 V Voltage CWD, CRST, WD–EN, SETx, WDI,  MR (2), WDO (Push Pull) –0.3 VDD+0.3 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/SF_WMY9TRSL1 V   WDO (Open Drain) –0.3 6.5 Current  WDO pin –20 20 mA Temperature #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER2 Operating ambient temperature, TA –40 125 ℃ Temperature Storage, Tstg –65 150 over operating free-air temperature range, unless otherwise noted#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER1 MIN MAX UNIT Voltage VDD –0.3 6.5 V Voltage CWD, CRST, WD–EN, SETx, WDI,  MR (2), WDO (Push Pull) –0.3 VDD+0.3 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/SF_WMY9TRSL1 V   WDO (Open Drain) –0.3 6.5 Current  WDO pin –20 20 mA Temperature #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER2 Operating ambient temperature, TA –40 125 ℃ Temperature Storage, Tstg –65 150 MIN MAX UNIT MIN MAX UNIT MINMAXUNIT Voltage VDD –0.3 6.5 V Voltage CWD, CRST, WD–EN, SETx, WDI,  MR (2), WDO (Push Pull) –0.3 VDD+0.3 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/SF_WMY9TRSL1 V   WDO (Open Drain) –0.3 6.5 Current  WDO pin –20 20 mA Temperature #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER2 Operating ambient temperature, TA –40 125 ℃ Temperature Storage, Tstg –65 150 Voltage VDD –0.3 6.5 V VoltageVDD–0.36.5V Voltage CWD, CRST, WD–EN, SETx, WDI,  MR (2), WDO (Push Pull) –0.3 VDD+0.3 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/SF_WMY9TRSL1 V VoltageCWD, CRST, WD–EN, SETx, WDI,  MR (2), WDO (Push Pull)WDRSTMR(2)WDO–0.3VDD+0.3 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/SF_WMY9TRSL1 DD#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/SF_WMY9TRSL1V   WDO (Open Drain) –0.3 6.5   WDO (Open Drain) WDO (Open Drain)WDO–0.36.5 Current  WDO pin –20 20 mA Current WDO pinWDO–2020mA Temperature #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER2 Operating ambient temperature, TA –40 125 ℃ Temperature #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER2 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER2Operating ambient temperature, TA A–40125℃ Temperature Storage, Tstg –65 150 TemperatureStorage, Tstg stg–65150 Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR.  The absolute maximum rating is (VDD + 0.3) V or 6.5 V, whichever is smaller As a result of the low dissipated power in this device, it is assumed that TJ = TA. Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.Absolute Maximum RatingRecommended Operating ConditionIf the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR. MRDDDDMRThe absolute maximum rating is (VDD + 0.3) V or 6.5 V, whichever is smallerAs a result of the low dissipated power in this device, it is assumed that TJ = TA.JA ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244048/A_SUPERVISOR_VVCM_3_ESD_RATINGS_AUTOMOTIVE_FOOTER1 ±2000 V Charged device model (CDM), per AEC Q100-011 ±750 AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244048/A_SUPERVISOR_VVCM_3_ESD_RATINGS_AUTOMOTIVE_FOOTER1 ±2000 V Charged device model (CDM), per AEC Q100-011 ±750 AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244048/A_SUPERVISOR_VVCM_3_ESD_RATINGS_AUTOMOTIVE_FOOTER1 ±2000 V Charged device model (CDM), per AEC Q100-011 ±750 VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244048/A_SUPERVISOR_VVCM_3_ESD_RATINGS_AUTOMOTIVE_FOOTER1 ±2000 V Charged device model (CDM), per AEC Q100-011 ±750 VALUE UNIT VALUE UNIT VALUEUNIT V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244048/A_SUPERVISOR_VVCM_3_ESD_RATINGS_AUTOMOTIVE_FOOTER1 ±2000 V Charged device model (CDM), per AEC Q100-011 ±750 V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244048/A_SUPERVISOR_VVCM_3_ESD_RATINGS_AUTOMOTIVE_FOOTER1 ±2000 V V(ESD) (ESD)Electrostatic dischargeHuman body model (HBM), per AEC Q100-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244048/A_SUPERVISOR_VVCM_3_ESD_RATINGS_AUTOMOTIVE_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244048/A_SUPERVISOR_VVCM_3_ESD_RATINGS_AUTOMOTIVE_FOOTER1±2000V Charged device model (CDM), per AEC Q100-011 ±750 Charged device model (CDM), per AEC Q100-011±750 AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Voltage VDD (Active Low output) 0.9 6 V CWD, CRST, WD–EN, SETx, WDI, MR (1) 0 VDD WDO (Open Drain) 0 6 WDO (Push Pull) 0 VDD Current WDO pin current –5 5 mA CRST CRST pin capacitor range 1.5 1800 nF CWD CWD pin capacitor range 1.5 1000 nF TA Operating ambient temperature –40 125 ℃ If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR. VMR should not be higher than VDD. Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Voltage VDD (Active Low output) 0.9 6 V CWD, CRST, WD–EN, SETx, WDI, MR (1) 0 VDD WDO (Open Drain) 0 6 WDO (Push Pull) 0 VDD Current WDO pin current –5 5 mA CRST CRST pin capacitor range 1.5 1800 nF CWD CWD pin capacitor range 1.5 1000 nF TA Operating ambient temperature –40 125 ℃ If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR. VMR should not be higher than VDD. over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Voltage VDD (Active Low output) 0.9 6 V CWD, CRST, WD–EN, SETx, WDI, MR (1) 0 VDD WDO (Open Drain) 0 6 WDO (Push Pull) 0 VDD Current WDO pin current –5 5 mA CRST CRST pin capacitor range 1.5 1800 nF CWD CWD pin capacitor range 1.5 1000 nF TA Operating ambient temperature –40 125 ℃ over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Voltage VDD (Active Low output) 0.9 6 V CWD, CRST, WD–EN, SETx, WDI, MR (1) 0 VDD WDO (Open Drain) 0 6 WDO (Push Pull) 0 VDD Current WDO pin current –5 5 mA CRST CRST pin capacitor range 1.5 1800 nF CWD CWD pin capacitor range 1.5 1000 nF TA Operating ambient temperature –40 125 ℃ MIN NOM MAX UNIT MIN NOM MAX UNIT MINNOMMAXUNIT Voltage VDD (Active Low output) 0.9 6 V CWD, CRST, WD–EN, SETx, WDI, MR (1) 0 VDD WDO (Open Drain) 0 6 WDO (Push Pull) 0 VDD Current WDO pin current –5 5 mA CRST CRST pin capacitor range 1.5 1800 nF CWD CWD pin capacitor range 1.5 1000 nF TA Operating ambient temperature –40 125 ℃ Voltage VDD (Active Low output) 0.9 6 V VoltageVDD (Active Low output)0.96V CWD, CRST, WD–EN, SETx, WDI, MR (1) 0 VDD CWD, CRST, WD–EN, SETx, WDI, MR (1) WDRSTMR(1)0VDD WDO (Open Drain) 0 6 WDO (Open Drain)WDO06 WDO (Push Pull) 0 VDD WDO (Push Pull)WDO0VDD Current WDO pin current –5 5 mA Current WDO pin currentWDO–55mA CRST CRST pin capacitor range 1.5 1800 nF CRST RSTCRST pin capacitor rangeRST1.51800nF CWD CWD pin capacitor range 1.5 1000 nF CWD WDCWD pin capacitor rangeWD1.51000nF TA Operating ambient temperature –40 125 ℃ TA AOperating ambient temperature–40125℃ If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR. VMR should not be higher than VDD. If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR. VMR should not be higher than VDD. MRDDDDMRMRDD. Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244050/A_SUPERVISOR_VVCM_5_THERMAL_FOOTER1 TPS3436-Q1 UNIT DDF (SOT23-8) 8 PINS RθJA Junction-to-ambient thermal resistance 175.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 94.7 °C/W RθJB Junction-to-board thermal resistance 92.4 °C/W ψJT Junction-to-top characterization parameter 8.4 °C/W ψJB Junction-to-board characterization parameter 91.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244050/A_SUPERVISOR_VVCM_5_THERMAL_FOOTER1 TPS3436-Q1 UNIT DDF (SOT23-8) 8 PINS RθJA Junction-to-ambient thermal resistance 175.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 94.7 °C/W RθJB Junction-to-board thermal resistance 92.4 °C/W ψJT Junction-to-top characterization parameter 8.4 °C/W ψJB Junction-to-board characterization parameter 91.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244050/A_SUPERVISOR_VVCM_5_THERMAL_FOOTER1 TPS3436-Q1 UNIT DDF (SOT23-8) 8 PINS RθJA Junction-to-ambient thermal resistance 175.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 94.7 °C/W RθJB Junction-to-board thermal resistance 92.4 °C/W ψJT Junction-to-top characterization parameter 8.4 °C/W ψJB Junction-to-board characterization parameter 91.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244050/A_SUPERVISOR_VVCM_5_THERMAL_FOOTER1 TPS3436-Q1 UNIT DDF (SOT23-8) 8 PINS RθJA Junction-to-ambient thermal resistance 175.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 94.7 °C/W RθJB Junction-to-board thermal resistance 92.4 °C/W ψJT Junction-to-top characterization parameter 8.4 °C/W ψJB Junction-to-board characterization parameter 91.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244050/A_SUPERVISOR_VVCM_5_THERMAL_FOOTER1 TPS3436-Q1 UNIT DDF (SOT23-8) 8 PINS THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244050/A_SUPERVISOR_VVCM_5_THERMAL_FOOTER1 TPS3436-Q1 UNIT THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244050/A_SUPERVISOR_VVCM_5_THERMAL_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244050/A_SUPERVISOR_VVCM_5_THERMAL_FOOTER1 TPS3436-Q1 TPS3436-Q1UNIT DDF (SOT23-8) DDF (SOT23-8) 8 PINS 8 PINS RθJA Junction-to-ambient thermal resistance 175.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 94.7 °C/W RθJB Junction-to-board thermal resistance 92.4 °C/W ψJT Junction-to-top characterization parameter 8.4 °C/W ψJB Junction-to-board characterization parameter 91.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W RθJA Junction-to-ambient thermal resistance 175.3 °C/W RθJA θJAJunction-to-ambient thermal resistance175.3°C/W RθJC(top) Junction-to-case (top) thermal resistance 94.7 °C/W RθJC(top) θJC(top)Junction-to-case (top) thermal resistance94.7°C/W RθJB Junction-to-board thermal resistance 92.4 °C/W RθJB θJBJunction-to-board thermal resistance92.4°C/W ψJT Junction-to-top characterization parameter 8.4 °C/W ψJT JTJunction-to-top characterization parameter8.4°C/W ψJB Junction-to-board characterization parameter 91.9 °C/W ψJB JBJunction-to-board characterization parameter91.9°C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W RθJC(bot) θJC(bot)Junction-to-case (bottom) thermal resistanceN/A°C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.Semiconductor and IC Package Thermal Metrics Electrical Characteristics At 1.04 V ≤ VDD ≤ 6 V, MR = Open, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT COMMON PARAMETERS VDD Input supply voltage Active LOW output 1.04 6 V IDD Supply current into VDD pin #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245017/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER5_SF2_SF1 TA = –40℃ to 85℃  0.25 0.8 µA 0.25 3 VIL Low level input voltage WD–EN, WDI, SETx, MR (3) 0.3VDD V VIH High level input voltage WD–EN, WDI, SETx, MR (3) 0.7VDD V R MR Manual reset internal pull-up resistance 100 kΩ WDO (Open-drain active-low) VOL Low level output voltage  VDD =1.5 VIOUT(Sink) = 500 µA 300 mV VDD = 3.3 VIOUT(Sink) = 2 mA 300 Ilkg(OD) Open-Drain output leakage current VDD = VPULLUP = 6VTA = –40℃ to 85℃ 10 30 nA VDD = VPULLUP = 6V 10 60 nA WDO (Push-pull active-low) VPOR Power on WDO voltage (5) VOH(min) = 0.8 VDDIout (source) = 15 µA 900 mV VOL Low level output voltage  VDD = 1.5 VIOUT(Sink) = 500 µA 300 mV VDD = 3.3 VIOUT(Sink) = 2 mA 300 VOH High level output voltage  VDD = 1.8 VIOUT(Source) = 500 µA 0.8VDD V VDD = 3.3 VIOUT(Source) = 500 µA 0.8VDD VDD = 6 VIOUT(Source) = 2 mA 0.8VDD If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR. VPOR is the minimum VDD voltage level for a controlled output state Electrical Characteristics At 1.04 V ≤ VDD ≤ 6 V, MR = Open, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT COMMON PARAMETERS VDD Input supply voltage Active LOW output 1.04 6 V IDD Supply current into VDD pin #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245017/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER5_SF2_SF1 TA = –40℃ to 85℃  0.25 0.8 µA 0.25 3 VIL Low level input voltage WD–EN, WDI, SETx, MR (3) 0.3VDD V VIH High level input voltage WD–EN, WDI, SETx, MR (3) 0.7VDD V R MR Manual reset internal pull-up resistance 100 kΩ WDO (Open-drain active-low) VOL Low level output voltage  VDD =1.5 VIOUT(Sink) = 500 µA 300 mV VDD = 3.3 VIOUT(Sink) = 2 mA 300 Ilkg(OD) Open-Drain output leakage current VDD = VPULLUP = 6VTA = –40℃ to 85℃ 10 30 nA VDD = VPULLUP = 6V 10 60 nA WDO (Push-pull active-low) VPOR Power on WDO voltage (5) VOH(min) = 0.8 VDDIout (source) = 15 µA 900 mV VOL Low level output voltage  VDD = 1.5 VIOUT(Sink) = 500 µA 300 mV VDD = 3.3 VIOUT(Sink) = 2 mA 300 VOH High level output voltage  VDD = 1.8 VIOUT(Source) = 500 µA 0.8VDD V VDD = 3.3 VIOUT(Source) = 500 µA 0.8VDD VDD = 6 VIOUT(Source) = 2 mA 0.8VDD If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR. VPOR is the minimum VDD voltage level for a controlled output state At 1.04 V ≤ VDD ≤ 6 V, MR = Open, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT COMMON PARAMETERS VDD Input supply voltage Active LOW output 1.04 6 V IDD Supply current into VDD pin #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245017/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER5_SF2_SF1 TA = –40℃ to 85℃  0.25 0.8 µA 0.25 3 VIL Low level input voltage WD–EN, WDI, SETx, MR (3) 0.3VDD V VIH High level input voltage WD–EN, WDI, SETx, MR (3) 0.7VDD V R MR Manual reset internal pull-up resistance 100 kΩ WDO (Open-drain active-low) VOL Low level output voltage  VDD =1.5 VIOUT(Sink) = 500 µA 300 mV VDD = 3.3 VIOUT(Sink) = 2 mA 300 Ilkg(OD) Open-Drain output leakage current VDD = VPULLUP = 6VTA = –40℃ to 85℃ 10 30 nA VDD = VPULLUP = 6V 10 60 nA WDO (Push-pull active-low) VPOR Power on WDO voltage (5) VOH(min) = 0.8 VDDIout (source) = 15 µA 900 mV VOL Low level output voltage  VDD = 1.5 VIOUT(Sink) = 500 µA 300 mV VDD = 3.3 VIOUT(Sink) = 2 mA 300 VOH High level output voltage  VDD = 1.8 VIOUT(Source) = 500 µA 0.8VDD V VDD = 3.3 VIOUT(Source) = 500 µA 0.8VDD VDD = 6 VIOUT(Source) = 2 mA 0.8VDD At 1.04 V ≤ VDD ≤ 6 V, MR = Open, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃DDMR WDOpull-upLOADA PARAMETER TEST CONDITIONS MIN TYP MAX UNIT COMMON PARAMETERS VDD Input supply voltage Active LOW output 1.04 6 V IDD Supply current into VDD pin #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245017/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER5_SF2_SF1 TA = –40℃ to 85℃  0.25 0.8 µA 0.25 3 VIL Low level input voltage WD–EN, WDI, SETx, MR (3) 0.3VDD V VIH High level input voltage WD–EN, WDI, SETx, MR (3) 0.7VDD V R MR Manual reset internal pull-up resistance 100 kΩ WDO (Open-drain active-low) VOL Low level output voltage  VDD =1.5 VIOUT(Sink) = 500 µA 300 mV VDD = 3.3 VIOUT(Sink) = 2 mA 300 Ilkg(OD) Open-Drain output leakage current VDD = VPULLUP = 6VTA = –40℃ to 85℃ 10 30 nA VDD = VPULLUP = 6V 10 60 nA WDO (Push-pull active-low) VPOR Power on WDO voltage (5) VOH(min) = 0.8 VDDIout (source) = 15 µA 900 mV VOL Low level output voltage  VDD = 1.5 VIOUT(Sink) = 500 µA 300 mV VDD = 3.3 VIOUT(Sink) = 2 mA 300 VOH High level output voltage  VDD = 1.8 VIOUT(Source) = 500 µA 0.8VDD V VDD = 3.3 VIOUT(Source) = 500 µA 0.8VDD VDD = 6 VIOUT(Source) = 2 mA 0.8VDD PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT COMMON PARAMETERS VDD Input supply voltage Active LOW output 1.04 6 V IDD Supply current into VDD pin #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245017/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER5_SF2_SF1 TA = –40℃ to 85℃  0.25 0.8 µA 0.25 3 VIL Low level input voltage WD–EN, WDI, SETx, MR (3) 0.3VDD V VIH High level input voltage WD–EN, WDI, SETx, MR (3) 0.7VDD V R MR Manual reset internal pull-up resistance 100 kΩ WDO (Open-drain active-low) VOL Low level output voltage  VDD =1.5 VIOUT(Sink) = 500 µA 300 mV VDD = 3.3 VIOUT(Sink) = 2 mA 300 Ilkg(OD) Open-Drain output leakage current VDD = VPULLUP = 6VTA = –40℃ to 85℃ 10 30 nA VDD = VPULLUP = 6V 10 60 nA WDO (Push-pull active-low) VPOR Power on WDO voltage (5) VOH(min) = 0.8 VDDIout (source) = 15 µA 900 mV VOL Low level output voltage  VDD = 1.5 VIOUT(Sink) = 500 µA 300 mV VDD = 3.3 VIOUT(Sink) = 2 mA 300 VOH High level output voltage  VDD = 1.8 VIOUT(Source) = 500 µA 0.8VDD V VDD = 3.3 VIOUT(Source) = 500 µA 0.8VDD VDD = 6 VIOUT(Source) = 2 mA 0.8VDD COMMON PARAMETERS COMMON PARAMETERS VDD Input supply voltage Active LOW output 1.04 6 V VDD DDInput supply voltageActive LOW output1.046V IDD Supply current into VDD pin #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245017/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER5_SF2_SF1 TA = –40℃ to 85℃  0.25 0.8 µA IDD DDSupply current into VDD pin #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245017/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER5_SF2_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245017/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER5_SF2_SF1TA = –40℃ to 85℃ A0.250.8µA 0.25 3 0.253 VIL Low level input voltage WD–EN, WDI, SETx, MR (3) 0.3VDD V VIL ILLow level input voltage WD–EN, WDI, SETx, MR (3) MR(3)0.3VDD DDV VIH High level input voltage WD–EN, WDI, SETx, MR (3) 0.7VDD V VIH IHHigh level input voltage WD–EN, WDI, SETx, MR (3) MR(3)0.7VDD DDV R MR Manual reset internal pull-up resistance 100 kΩ R MR MR MRManual reset internal pull-up resistance100kΩ WDO (Open-drain active-low) WDO (Open-drain active-low)WDO VOL Low level output voltage  VDD =1.5 VIOUT(Sink) = 500 µA 300 mV VOL OLLow level output voltage VDD =1.5 VIOUT(Sink) = 500 µADDOUT(Sink)300mV VDD = 3.3 VIOUT(Sink) = 2 mA 300 VDD = 3.3 VIOUT(Sink) = 2 mADDOUT(Sink)300 Ilkg(OD) Open-Drain output leakage current VDD = VPULLUP = 6VTA = –40℃ to 85℃ 10 30 nA Ilkg(OD) lkg(OD)Open-Drain output leakage currentVDD = VPULLUP = 6VTA = –40℃ to 85℃DDPULLUPA1030nA VDD = VPULLUP = 6V 10 60 nA VDD = VPULLUP = 6VDDPULLUP1060nA WDO (Push-pull active-low) WDO (Push-pull active-low)WDO VPOR Power on WDO voltage (5) VOH(min) = 0.8 VDDIout (source) = 15 µA 900 mV VPOR PORPower on WDO voltage (5) WDO(5)VOH(min) = 0.8 VDDIout (source) = 15 µAOH(min)out (source)900mV VOL Low level output voltage  VDD = 1.5 VIOUT(Sink) = 500 µA 300 mV VOL OLLow level output voltage VDD = 1.5 VIOUT(Sink) = 500 µADDOUT(Sink)300mV VDD = 3.3 VIOUT(Sink) = 2 mA 300 VDD = 3.3 VIOUT(Sink) = 2 mADDOUT(Sink)300 VOH High level output voltage  VDD = 1.8 VIOUT(Source) = 500 µA 0.8VDD V VOH OHHigh level output voltage VDD = 1.8 VIOUT(Source) = 500 µADD OUT(Source)0.8VDD DDV VDD = 3.3 VIOUT(Source) = 500 µA 0.8VDD VDD = 3.3 VIOUT(Source) = 500 µADD OUT(Source)0.8VDD DD VDD = 6 VIOUT(Source) = 2 mA 0.8VDD VDD = 6 VIOUT(Source) = 2 mADD OUT(Source)0.8VDD DD If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR. VPOR is the minimum VDD voltage level for a controlled output state If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR.MRDDDD MRVPOR is the minimum VDD voltage level for a controlled output statePORDD Timing Requirements At 1.04 V ≤ VDD ≤ 6 V, MR = Open, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output RESET / WDO load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t MR_PW MR pin pulse duration to assert output 100 ns tP-WD WDI pulse duration to start next frame #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245016/SFKSOT305GOW 500 ns tHD-WDEN WD–EN hold time to enable or disable WD operation #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245016/SFKSOT305GOW 200 µs tHD-SETx SETx hold time to change WD timer setting #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245016/SFKSOT305GOW 150 µs tWC Watchdog close window time period Orderable Option TPS3436xxB 0.8 1 1.2 ms Orderable Option TPS3436xxC 4 5 6 Orderable Option TPS3436xxD 9 10 11 Orderable Option TPS3436xxE 18 20 22 Orderable Option TPS3436xxF 45 50 55 Orderable Option TPS3436xxG 90 100 110 Orderable Option TPS3436xxH 180 200 220 Orderable Option TPS3436xxI 0.9 1 1.1 s Orderable Option TPS3436xxJ 1.26 1.4 1.54 Orderable Option TPS3436xxK 1.44 1.6 1.76 Orderable Option TPS3436xxL 9 10 11 Orderable Option TPS3436xxM 45 50 55 Orderable Option TPS3436xxN 90 100 110 tWO Watchdog open window time period SETx pin decide multipler n (n-1) X tWC ms Not production tested Timing Requirements At 1.04 V ≤ VDD ≤ 6 V, MR = Open, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output RESET / WDO load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t MR_PW MR pin pulse duration to assert output 100 ns tP-WD WDI pulse duration to start next frame #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245016/SFKSOT305GOW 500 ns tHD-WDEN WD–EN hold time to enable or disable WD operation #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245016/SFKSOT305GOW 200 µs tHD-SETx SETx hold time to change WD timer setting #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245016/SFKSOT305GOW 150 µs tWC Watchdog close window time period Orderable Option TPS3436xxB 0.8 1 1.2 ms Orderable Option TPS3436xxC 4 5 6 Orderable Option TPS3436xxD 9 10 11 Orderable Option TPS3436xxE 18 20 22 Orderable Option TPS3436xxF 45 50 55 Orderable Option TPS3436xxG 90 100 110 Orderable Option TPS3436xxH 180 200 220 Orderable Option TPS3436xxI 0.9 1 1.1 s Orderable Option TPS3436xxJ 1.26 1.4 1.54 Orderable Option TPS3436xxK 1.44 1.6 1.76 Orderable Option TPS3436xxL 9 10 11 Orderable Option TPS3436xxM 45 50 55 Orderable Option TPS3436xxN 90 100 110 tWO Watchdog open window time period SETx pin decide multipler n (n-1) X tWC ms Not production tested At 1.04 V ≤ VDD ≤ 6 V, MR = Open, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output RESET / WDO load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t MR_PW MR pin pulse duration to assert output 100 ns tP-WD WDI pulse duration to start next frame #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245016/SFKSOT305GOW 500 ns tHD-WDEN WD–EN hold time to enable or disable WD operation #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245016/SFKSOT305GOW 200 µs tHD-SETx SETx hold time to change WD timer setting #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245016/SFKSOT305GOW 150 µs tWC Watchdog close window time period Orderable Option TPS3436xxB 0.8 1 1.2 ms Orderable Option TPS3436xxC 4 5 6 Orderable Option TPS3436xxD 9 10 11 Orderable Option TPS3436xxE 18 20 22 Orderable Option TPS3436xxF 45 50 55 Orderable Option TPS3436xxG 90 100 110 Orderable Option TPS3436xxH 180 200 220 Orderable Option TPS3436xxI 0.9 1 1.1 s Orderable Option TPS3436xxJ 1.26 1.4 1.54 Orderable Option TPS3436xxK 1.44 1.6 1.76 Orderable Option TPS3436xxL 9 10 11 Orderable Option TPS3436xxM 45 50 55 Orderable Option TPS3436xxN 90 100 110 tWO Watchdog open window time period SETx pin decide multipler n (n-1) X tWC ms At 1.04 V ≤ VDD ≤ 6 V, MR = Open, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output RESET / WDO load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃DDMR WDOpull-upLOADA PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t MR_PW MR pin pulse duration to assert output 100 ns tP-WD WDI pulse duration to start next frame #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245016/SFKSOT305GOW 500 ns tHD-WDEN WD–EN hold time to enable or disable WD operation #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245016/SFKSOT305GOW 200 µs tHD-SETx SETx hold time to change WD timer setting #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245016/SFKSOT305GOW 150 µs tWC Watchdog close window time period Orderable Option TPS3436xxB 0.8 1 1.2 ms Orderable Option TPS3436xxC 4 5 6 Orderable Option TPS3436xxD 9 10 11 Orderable Option TPS3436xxE 18 20 22 Orderable Option TPS3436xxF 45 50 55 Orderable Option TPS3436xxG 90 100 110 Orderable Option TPS3436xxH 180 200 220 Orderable Option TPS3436xxI 0.9 1 1.1 s Orderable Option TPS3436xxJ 1.26 1.4 1.54 Orderable Option TPS3436xxK 1.44 1.6 1.76 Orderable Option TPS3436xxL 9 10 11 Orderable Option TPS3436xxM 45 50 55 Orderable Option TPS3436xxN 90 100 110 tWO Watchdog open window time period SETx pin decide multipler n (n-1) X tWC ms PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT t MR_PW MR pin pulse duration to assert output 100 ns tP-WD WDI pulse duration to start next frame #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245016/SFKSOT305GOW 500 ns tHD-WDEN WD–EN hold time to enable or disable WD operation #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245016/SFKSOT305GOW 200 µs tHD-SETx SETx hold time to change WD timer setting #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245016/SFKSOT305GOW 150 µs tWC Watchdog close window time period Orderable Option TPS3436xxB 0.8 1 1.2 ms Orderable Option TPS3436xxC 4 5 6 Orderable Option TPS3436xxD 9 10 11 Orderable Option TPS3436xxE 18 20 22 Orderable Option TPS3436xxF 45 50 55 Orderable Option TPS3436xxG 90 100 110 Orderable Option TPS3436xxH 180 200 220 Orderable Option TPS3436xxI 0.9 1 1.1 s Orderable Option TPS3436xxJ 1.26 1.4 1.54 Orderable Option TPS3436xxK 1.44 1.6 1.76 Orderable Option TPS3436xxL 9 10 11 Orderable Option TPS3436xxM 45 50 55 Orderable Option TPS3436xxN 90 100 110 tWO Watchdog open window time period SETx pin decide multipler n (n-1) X tWC ms t MR_PW MR pin pulse duration to assert output 100 ns t MR_PW MR_PWMR MR pin pulse duration to assert outputMR100ns tP-WD WDI pulse duration to start next frame #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245016/SFKSOT305GOW 500 ns tP-WD P-WDWDI pulse duration to start next frame #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245016/SFKSOT305GOW #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245016/SFKSOT305GOW500ns tHD-WDEN WD–EN hold time to enable or disable WD operation #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245016/SFKSOT305GOW 200 µs tHD-WDEN HD-WDENWD–EN hold time to enable or disable WD operation #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245016/SFKSOT305GOW #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245016/SFKSOT305GOW200µs tHD-SETx SETx hold time to change WD timer setting #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245016/SFKSOT305GOW 150 µs tHD-SETx HD-SETxSETx hold time to change WD timer setting #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245016/SFKSOT305GOW #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245016/SFKSOT305GOW150µs tWC Watchdog close window time period Orderable Option TPS3436xxB 0.8 1 1.2 ms tWC WCWatchdog close window time periodOrderable Option TPS3436xxB0.811.2ms Orderable Option TPS3436xxC 4 5 6 Orderable Option TPS3436xxC456 Orderable Option TPS3436xxD 9 10 11 Orderable Option TPS3436xxD91011 Orderable Option TPS3436xxE 18 20 22 Orderable Option TPS3436xxE182022 Orderable Option TPS3436xxF 45 50 55 Orderable Option TPS3436xxF455055 Orderable Option TPS3436xxG 90 100 110 Orderable Option TPS3436xxG90100110 Orderable Option TPS3436xxH 180 200 220 Orderable Option TPS3436xxH180200220 Orderable Option TPS3436xxI 0.9 1 1.1 s Orderable Option TPS3436xxI0.911.1s Orderable Option TPS3436xxJ 1.26 1.4 1.54 Orderable Option TPS3436xxJ1.261.41.54 Orderable Option TPS3436xxK 1.44 1.6 1.76 Orderable Option TPS3436xxK1.441.61.76 Orderable Option TPS3436xxL 9 10 11 Orderable Option TPS3436xxL91011 Orderable Option TPS3436xxM 45 50 55 Orderable Option TPS3436xxM455055 Orderable Option TPS3436xxN 90 100 110 Orderable Option TPS3436xxN90100110 tWO Watchdog open window time period SETx pin decide multipler n (n-1) X tWC ms tWO WOWatchdog open window time periodSETx pin decide multipler n n (n-1) X tWC (n-1)WCms Not production tested Not production tested Switching Characteristics At 1.04 V ≤ VDD ≤ 6 V, MR = Open, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output RESET / WDO load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tSTRT Startup delay #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245018/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER1_SF1_SF2_SF1 CCRST pin = Open or NC  500 µs tSD Watchdog startup delay Orderable part number TPS3436xA, TPS343xG 0 ms Orderable part number TPS3436xB, TPS3436xH 180 200 220 Orderable part number TPS3436xC, TPS3436xI 450 500 550 Orderable part number TPS3436xD, TPS3436xJ 0.9 1 1.1 s Orderable part number TPS3436xE, TPS3436xK 4.5 5 5.5 Orderable part number TPS3436xF, TPS3436xL 9 10 11 tWDO Watchdog assert time delay Orderable part number TPS3436xxxxB 1.6 2 2.4 ms Orderable part number TPS3436xxxxC 9 10 11 ms Orderable part number TPS3436xxxxD 22.5 25 27.5 ms Orderable part number TPS3436xxxxE 45 50 55 ms Orderable part number TPS3436xxxxF 90 100 110 ms Orderable part number TPS3436xxxxG 180 200 220 ms Orderable part number TPS3436xxxxH 0.9 1 1.1 s Orderable part number TPS3436xxxxI 9 10 11 s t MR_WDO Propagation delay from MR low to WDO assertion VDD ≥ 1.25 V, MR = V MR_H to V MR_L 100 ns Specified by design parameter. Switching Characteristics At 1.04 V ≤ VDD ≤ 6 V, MR = Open, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output RESET / WDO load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tSTRT Startup delay #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245018/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER1_SF1_SF2_SF1 CCRST pin = Open or NC  500 µs tSD Watchdog startup delay Orderable part number TPS3436xA, TPS343xG 0 ms Orderable part number TPS3436xB, TPS3436xH 180 200 220 Orderable part number TPS3436xC, TPS3436xI 450 500 550 Orderable part number TPS3436xD, TPS3436xJ 0.9 1 1.1 s Orderable part number TPS3436xE, TPS3436xK 4.5 5 5.5 Orderable part number TPS3436xF, TPS3436xL 9 10 11 tWDO Watchdog assert time delay Orderable part number TPS3436xxxxB 1.6 2 2.4 ms Orderable part number TPS3436xxxxC 9 10 11 ms Orderable part number TPS3436xxxxD 22.5 25 27.5 ms Orderable part number TPS3436xxxxE 45 50 55 ms Orderable part number TPS3436xxxxF 90 100 110 ms Orderable part number TPS3436xxxxG 180 200 220 ms Orderable part number TPS3436xxxxH 0.9 1 1.1 s Orderable part number TPS3436xxxxI 9 10 11 s t MR_WDO Propagation delay from MR low to WDO assertion VDD ≥ 1.25 V, MR = V MR_H to V MR_L 100 ns Specified by design parameter. At 1.04 V ≤ VDD ≤ 6 V, MR = Open, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output RESET / WDO load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tSTRT Startup delay #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245018/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER1_SF1_SF2_SF1 CCRST pin = Open or NC  500 µs tSD Watchdog startup delay Orderable part number TPS3436xA, TPS343xG 0 ms Orderable part number TPS3436xB, TPS3436xH 180 200 220 Orderable part number TPS3436xC, TPS3436xI 450 500 550 Orderable part number TPS3436xD, TPS3436xJ 0.9 1 1.1 s Orderable part number TPS3436xE, TPS3436xK 4.5 5 5.5 Orderable part number TPS3436xF, TPS3436xL 9 10 11 tWDO Watchdog assert time delay Orderable part number TPS3436xxxxB 1.6 2 2.4 ms Orderable part number TPS3436xxxxC 9 10 11 ms Orderable part number TPS3436xxxxD 22.5 25 27.5 ms Orderable part number TPS3436xxxxE 45 50 55 ms Orderable part number TPS3436xxxxF 90 100 110 ms Orderable part number TPS3436xxxxG 180 200 220 ms Orderable part number TPS3436xxxxH 0.9 1 1.1 s Orderable part number TPS3436xxxxI 9 10 11 s t MR_WDO Propagation delay from MR low to WDO assertion VDD ≥ 1.25 V, MR = V MR_H to V MR_L 100 ns At 1.04 V ≤ VDD ≤ 6 V, MR = Open, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output RESET / WDO load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃DDMR WDOpull-upLOADA PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tSTRT Startup delay #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245018/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER1_SF1_SF2_SF1 CCRST pin = Open or NC  500 µs tSD Watchdog startup delay Orderable part number TPS3436xA, TPS343xG 0 ms Orderable part number TPS3436xB, TPS3436xH 180 200 220 Orderable part number TPS3436xC, TPS3436xI 450 500 550 Orderable part number TPS3436xD, TPS3436xJ 0.9 1 1.1 s Orderable part number TPS3436xE, TPS3436xK 4.5 5 5.5 Orderable part number TPS3436xF, TPS3436xL 9 10 11 tWDO Watchdog assert time delay Orderable part number TPS3436xxxxB 1.6 2 2.4 ms Orderable part number TPS3436xxxxC 9 10 11 ms Orderable part number TPS3436xxxxD 22.5 25 27.5 ms Orderable part number TPS3436xxxxE 45 50 55 ms Orderable part number TPS3436xxxxF 90 100 110 ms Orderable part number TPS3436xxxxG 180 200 220 ms Orderable part number TPS3436xxxxH 0.9 1 1.1 s Orderable part number TPS3436xxxxI 9 10 11 s t MR_WDO Propagation delay from MR low to WDO assertion VDD ≥ 1.25 V, MR = V MR_H to V MR_L 100 ns PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT tSTRT Startup delay #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245018/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER1_SF1_SF2_SF1 CCRST pin = Open or NC  500 µs tSD Watchdog startup delay Orderable part number TPS3436xA, TPS343xG 0 ms Orderable part number TPS3436xB, TPS3436xH 180 200 220 Orderable part number TPS3436xC, TPS3436xI 450 500 550 Orderable part number TPS3436xD, TPS3436xJ 0.9 1 1.1 s Orderable part number TPS3436xE, TPS3436xK 4.5 5 5.5 Orderable part number TPS3436xF, TPS3436xL 9 10 11 tWDO Watchdog assert time delay Orderable part number TPS3436xxxxB 1.6 2 2.4 ms Orderable part number TPS3436xxxxC 9 10 11 ms Orderable part number TPS3436xxxxD 22.5 25 27.5 ms Orderable part number TPS3436xxxxE 45 50 55 ms Orderable part number TPS3436xxxxF 90 100 110 ms Orderable part number TPS3436xxxxG 180 200 220 ms Orderable part number TPS3436xxxxH 0.9 1 1.1 s Orderable part number TPS3436xxxxI 9 10 11 s t MR_WDO Propagation delay from MR low to WDO assertion VDD ≥ 1.25 V, MR = V MR_H to V MR_L 100 ns tSTRT Startup delay #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245018/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER1_SF1_SF2_SF1 CCRST pin = Open or NC  500 µs tSTRT STRTStartup delay #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245018/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER1_SF1_SF2_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000245018/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER1_SF1_SF2_SF1CCRST pin = Open or NC CRST500µs tSD Watchdog startup delay Orderable part number TPS3436xA, TPS343xG 0 ms tSD SDWatchdog startup delayOrderable part number TPS3436xA, TPS343xG0ms Orderable part number TPS3436xB, TPS3436xH 180 200 220 Orderable part number TPS3436xB, TPS3436xH180200220 Orderable part number TPS3436xC, TPS3436xI 450 500 550 Orderable part number TPS3436xC, TPS3436xI450500550 Orderable part number TPS3436xD, TPS3436xJ 0.9 1 1.1 s Orderable part number TPS3436xD, TPS3436xJ0.911.1s Orderable part number TPS3436xE, TPS3436xK 4.5 5 5.5 Orderable part number TPS3436xE, TPS3436xK4.555.5 Orderable part number TPS3436xF, TPS3436xL 9 10 11 Orderable part number TPS3436xF, TPS3436xL91011 tWDO Watchdog assert time delay Orderable part number TPS3436xxxxB 1.6 2 2.4 ms tWDO WDOWatchdog assert time delayOrderable part number TPS3436xxxxB1.622.4ms Orderable part number TPS3436xxxxC 9 10 11 ms Orderable part number TPS3436xxxxC91011ms Orderable part number TPS3436xxxxD 22.5 25 27.5 ms Orderable part number TPS3436xxxxD22.52527.5ms Orderable part number TPS3436xxxxE 45 50 55 ms Orderable part number TPS3436xxxxE455055ms Orderable part number TPS3436xxxxF 90 100 110 ms Orderable part number TPS3436xxxxF90100110ms Orderable part number TPS3436xxxxG 180 200 220 ms Orderable part number TPS3436xxxxG180200220ms Orderable part number TPS3436xxxxH 0.9 1 1.1 s Orderable part number TPS3436xxxxH0.911.1s Orderable part number TPS3436xxxxI 9 10 11 s Orderable part number TPS3436xxxxI91011s t MR_WDO Propagation delay from MR low to WDO assertion VDD ≥ 1.25 V, MR = V MR_H to V MR_L 100 ns t MR_WDO MR_WDOMRPropagation delay from MR low to WDO assertionMRVDD ≥ 1.25 V, MR = V MR_H to V MR_L DDMR MR_H MR MR_LMR100ns Specified by design parameter. Specified by design parameter. Timing Diagrams * Added a footnote to for tINIT no Functional Timing Diagram Timing Diagrams * Added a footnote to for tINIT no * Added a footnote to for tINIT no * Added a footnote to for tINIT no *Added a footnote to for tINIT INITno Functional Timing Diagram Functional Timing Diagram Functional Timing Diagram Functional Timing Diagram Typical Characteristics all curves are taken at TA = 25°C (unless otherwise noted) Timer Accuracy vs Temperature Timer Accuracy Histogram tWC vs Capacitance tWDO vs Capacitance WDO VOL vs I sink, VDD = 1.5 V WDO VOL vs I sink, VDD = 3.3 V WDO VOH vs I source, VDD = 2.0 V WDO VOH vs I source, VDD = 6.0 V Supply Current vs Power-Supply Voltage Typical Characteristics all curves are taken at TA = 25°C (unless otherwise noted) Timer Accuracy vs Temperature Timer Accuracy Histogram tWC vs Capacitance tWDO vs Capacitance WDO VOL vs I sink, VDD = 1.5 V WDO VOL vs I sink, VDD = 3.3 V WDO VOH vs I source, VDD = 2.0 V WDO VOH vs I source, VDD = 6.0 V Supply Current vs Power-Supply Voltage all curves are taken at TA = 25°C (unless otherwise noted) Timer Accuracy vs Temperature Timer Accuracy Histogram tWC vs Capacitance tWDO vs Capacitance WDO VOL vs I sink, VDD = 1.5 V WDO VOL vs I sink, VDD = 3.3 V WDO VOH vs I source, VDD = 2.0 V WDO VOH vs I source, VDD = 6.0 V Supply Current vs Power-Supply Voltage all curves are taken at TA = 25°C (unless otherwise noted)A Timer Accuracy vs Temperature Timer Accuracy Histogram tWC vs Capacitance tWDO vs Capacitance WDO VOL vs I sink, VDD = 1.5 V WDO VOL vs I sink, VDD = 3.3 V WDO VOH vs I source, VDD = 2.0 V WDO VOH vs I source, VDD = 6.0 V Supply Current vs Power-Supply Voltage Timer Accuracy vs Temperature Timer Accuracy vs Temperature Timer Accuracy Histogram Timer Accuracy Histogram tWC vs Capacitance tWC vs CapacitanceWC tWDO vs Capacitance tWDO vs CapacitanceWDO WDO VOL vs I sink, VDD = 1.5 V WDO VOL vs I sink, VDD = 1.5 VOLsinkDD WDO VOL vs I sink, VDD = 3.3 V WDO VOL vs I sink, VDD = 3.3 VOLsinkDD WDO VOH vs I source, VDD = 2.0 V WDO VOH vs I source, VDD = 2.0 VOHsourceDD WDO VOH vs I source, VDD = 6.0 V WDO VOH vs I source, VDD = 6.0 VOHsourceDD Supply Current vs Power-Supply Voltage Supply Current vs Power-Supply Voltage Detailed Description Overview The TPS3436-Q1 is a high-accuracy window watchdog timer device. The device family supports multiple features related to watchdog operation in a compact 8 pin SOT23 package. The devices are available in 3 different pinout configurations. Each pinout offers access to different features to meet the various application requirements. The device family is rated for -Q100 applications. Functional Block Diagrams Pinout Option A Pinout Option B Pinout Option C Feature Description Window Watchdog Timer The TPS3436-Q1 offers high precision window watchdog timer monitoring. The device is available in multiple pinout options A to C which support multiple features to meet ever expanding needs of various applications. Ensure a correct pinout is selected to meet the application needs. The window watchdog is active when the VDD voltage is higher than the VDDMIN, MR voltage is held higher than 0.7 x VDD and watchdog is enabled. TPS3436-Q1 family offers various startup time delay options to ensure enough time is available for the host to complete boot operation. Please refer section for additional details. The window watchdog timer frame consists of two windows namely close window (tWC) followed by open window (tWO). The device monitors the WDI pin for falling edge. User is expected to provide a valid falling edge on WDI pin in the open window. Refer to arrive at the relevant close window and open window values needed for application. The timer value is reset when a valid falling edge is detected on WDI pin in the tWO time duration. An early fault is reported if a WDI falling edge is detected in close window. A late fault is reported if WDI falling edge is not detected in both close and open window. The device asserts WDO output for time tWDO in event of watchdog fault. Refer to arrive at the relevant tWDO value needed for application. shows the basic operation for window watchdog timer operation. The TPS3436-Q1 watchdog functionality supports multiple features. Details are available in following sub sections. Window Watchdog Timer Operation tWC (Close Window) Timer The window watchdog frame consists of two sub frames tWC followed by tWO. The host is not expected to drive valid WDI transition during tWC time. A valid WDI transition during tWC frame results in early fault condition and the WDO output is asserted. The tWC timer for TPS3436-Q1 can be set using an external capacitor connected between CWD pin and GND pin. This feature is available with pinout options A or B. Applications which are space constrained or need timer values which meet offered timer options, can benefit when using pinout option C. The TPS3436-Q1 offers multiple fixed timer options ranging from 1 msec up-to 100 sec. The TPS3436-Q1 when using capacitance based timer, senses the capacitance value during the power up. The capacitor is charged and discharged with known internal current source for one cycle to sense the capacitance value. The sensed value is used to arrive at tWC timer for the watchdog operation. This unique implementation helps reduce the continuous charge and discharge current for the capacitor, thus reducing overall current consumption. Continuous charge and discharge of capacitance creates wider dead time (no watchdog monitor functionality) when capacitor is discharging. The dead time is higher for high value of capacitance. The unique implementation of TPS3436-Q1 helps avoid the dead time as the capacitance is not continuously charging or discharging under normal operation. Ensure CCWD is < 200 x CCRST for accurate calibration of capacitance. The close time window is decided based on SETx pin combination and the CWD capacitance. #GUID-D3B3A4B6-F3FF-43A2-9270-9617951C20C1/TABLE_EPC_QP1_DVB to #GUID-D3B3A4B6-F3FF-43A2-9270-9617951C20C1/TABLE_MHQ_NQ1_DVB highlights the relationship between tWC in second and CWD capacitance in farad. The tWC timer is 20% accurate for an ideal capacitor. Accuracy of the capacitance will have additional impact on the tWC time. Ensure the capacitance meets the recommended operating range. Capacitance outside the recommended range can lead to incorrect operation of the device. tWC Equation 1 SET Pin (Pin Configuration A) SET PIN VALUE EQUATION 0 tWC (sec) = 79.2 x 106 x CCWD (F) 1 tWC (sec) = 39.6 x 106 x CCWD (F) tWC Equation 2 SET Pin, WD-EN Not Available (Pin Configuration B) SET PIN VALUE EQUATION 00 tWC (sec) = 79.2 x 106 x CCWD (F) 01 Watchdog disabled 10 tWC (sec) = 39.6 x 106 x CCWD (F) 11 tWC (sec) = 9.9 x 106 x CCWD (F) The TPS3436-Q1 also offers wide selection of high accuracy fixed tWC timer options starting from 1 msec to 100 sec including various industry standard values. The TPS3436-Q1 fixed time options are ±10% accurate for tWC ≥ 10 msec. For tWC < 10 msec, the accuracy is ±20%. tWC value relevant to application can be identified from the orderable part number. Refer to identify mapping of orderable part number to tWC value. tWO (Open Window) Timer The window watchdog frame consists of two sub frames tWC followed by tWO. The host is expected to drive valid WDI transition during tWO time. A valid WDI transition before beginning of tWO frame causes early fault condition. Failure to offer valid WDI transition during tWC and tWO frames results in late fault condition. When a fault condition is detected the WDO output is asserted. The tWO value is derived using tWC value and the window open time ratio value n. Equation highlights the relationship between tWO and tWC. Refer to select available ratio options. tWO = (n - 1) x tWC Each orderable can offer up to 3 ratio options based on the available SET pins. Refer to identify mapping of ratio value to SET pin control. The maximum tWO value is limited to 640 second. Ensure selected tWC and ratio combination does not lead to tWO value greater than 640 second. Watchdog Enable Disable Operation The TPS3436-Q1 supports watchdog enable or disable functionality. This functionality is critical for different use cases as listed below. Disable watchdog during firmware update to avoid host RESET. Disable watchdog during software step-by-step debug operation. Disable watchdog when performing critical task to avoid watchdog error interrupt. Keep watchdog disabled until host boots up. The TPS3436-Q1 supports watchdog enable or disable functionality through either WD-EN pin (pin configuration C) or SET[1:0] = 0b'01 (pin configuration B) logic combination. For a given pinout only one of these two methods is available for the user to disable watchdog operation. For a pinout which offers a WD-EN pin, the watchdog enable disable functionality is controlled by the logic state of WD-EN pin. Drive WD-EN = 1 to enable the watchdog operation or drive WD-EN = 0 to disable the watchdog operation. The WD-EN pin can be toggled any time during the device operation. The diagram shows timing behavior with WD-EN pin control. Watchdog Enable: WD-EN Pin Control SET[1:0] = 0b'01 combination can be used to disable watchdog operation with a pinout which offers SET1 and SET0 pins, but does not include WD-EN pin. The SET pin logic states can be changed at any time during watchdog operation. Refer section for additional details regarding SET[1:0] pin behavior. Pinout options A, B offer watchdog timer control using a capacitance connected between CWD and GND pin. A capacitance value higher than recommended or connect to GND leads to watchdog functionality getting disabled. Capacitance based disable operation overrides the other two options mentioned above. Changing capacitance on the fly does not enable or disable watchdog operation. A power supply recycle is needed to detect change in capacitance. Ongoing watchdog frame is terminated when watchdog is disabled. WDO stays deasserted when watchdog operation is disabled. When enabled the device immediately enters tWC frame and start watchdog monitoring operation. tSD Watchdog Start Up Delay The TPS3436-Q1 supports watchdog startup delay feature. This feature is activated after power up or after WDO assert event. When tSD frame is active, the device monitors the WDI pin but the WDO output is not asserted. This feature allows time for the host complete boot process before watchdog monitoring can take over. The start up delay helps avoid unexpected WDO assert events during boot. The tSD time is predetermined based on the device part number selected. Refer section for details to map the part number to tSD time. Pinout option A, B are available only in no delay or 10 sec start up delay options. The tSD frame is complete when the time duration selected for tSD is over or host provides a valid transition on the WDI pin. The host must provide a valid transition on the WDI pin during tSD time. The device exits the tSD frame and enters watchdog monitoring phase after valid WDI transition. Failure to provide valid transition on WDI pin triggers the watchdog error by asserting the WDO output pin. The tSD frame is not initiated when the watchdog functionality is enabled using WD-EN pin or SET[1:0] pin combination as described in section. shows the operation for tSD time frame. tSD Frame Behavior SET Pin Behavior The TPS3436-Q1 offers one or two SET pins based on the pinout option selected. SET pins offer flexibility to the user to program the tWO timer on the fly to meet various application requirements. Typical use cases where SET pin can be used are Use wide open window timer when host is in sleep mode, change to small timeout operation when host is operational. Watchdog can be used to wake up the host after long duration to perform the application related activities before going back to sleep. Change to wide open window timer when performing system critical tasks to ensure watchdog does not interrupt the critical task. Change timer to application specified interval after the critical task is complete. The tWO timer value for the device is combination of tWC timer selection based on the CWD pin or fixed timer value along with SET pin logic level. The tWC timer value is decided based on the Watchdog Close Time selector in the section. The SET pin logic level is decoded during the device power up. The SET pin value can be changed any time during the operation. SETx pin change which leads to change of watchdog timer value or enable disable state, terminates the ongoing watchdog frame immediately. SETx pins can be updated when WDO output is asserted as well. The updated tWO timer value will be applied after output is deasserted and the tSD timer is over or terminated. For a pinout which offers only SET0 pin to the user, the tWO ratio value is decided based on the Watchdog Open Time Ratio selector field in the orderable part number. Refer for available options. showcases an example of the tWO values for different SET0 logic levels when using Watchdog Close Time setting as option D = 10 msec. tWO Values with SET0 Pin Only (Pin Configuration A) Watchdog Open Time Ratio Selection tWO SET0 = 0 SET0 = 1 A 10 msec 30 msec B 30 msec 70 msec C 70 msec 150 msec D 150 msec 310 msec E 310 msec 630 msec F 630 msec 1270 msec Pinout which offer both SET0 & SET1 pins to the user, the tWO ratio value is decided based on the Watchdog Open Time Ratio selector field in the orderable part number. Refer for available options. Two SETx pins offer 3 different time scaling options. The SET[1:0] = 0b'01 combination disables the watchdog operation. showcases an example of the tWO values for different SET[1:0] logic levels when using Watchdog Close Time setting as option G = 100 msec. The package pin out selected does not offer WD-EN pin. tWO Values with SET0 & SET1 Pins, WD-EN Pin Not Available (Pin Configuration B) Watchdog Open Time Ratio selection tWO SET[1:0] = 0b'00 SET[1:0] = 0b'01 SET[1:0] = 0b'10 SET[1:0] = 0b'11 A 100 msec Watchdog disable 300 msec 1500 msec B 300 msec Watchdog disable 700 msec 3100 msec C 700 msec Watchdog disable 1500 msec 6300 msec D 1500 msec Watchdog disable 3100 msec 12700 msec E 3100 msec Watchdog disable 6300 msec 25500 msec F 6300 msec Watchdog disable 12700 msec 51100 msec Example for Watchdog Close Time setting = 100 msec. Selected pinout option can offer WD-EN pin along with SET[1:0] pins (Pin Configuration C). With this pinout, the WD-EN pin controls watchdog enable and disable operation. The SET[1:0] = 0b'01 combination operates as SET[1:0] = 0b'00. Ensure the tWO value with SETx ratio does not exceed 640 sec. If a selection of close window timer and ratio results in tWO > 640 sec, the timer value will be restricted to 640 sec. to show the timing behavior with respect to SETx status changes. Watchdog Behavior with SETx Pin Status Watchdog Operation with 2 SET Pins Watchdog Operation with 1 SET Pin Manual RESET The TPS3436-Q1 supports manual reset functionality using MR pin. MR pin when driven with voltage lower than 0.3 x VDD, asserts the WDO output. The MR pin has 100 kΩ pull up to VDD. The MR pin can be left floating. The internal pull up makes sure the output is not asserted due to MR pin trigger. The output is deasserted after MR pin voltage rises above 0.7 x VDD voltage. Refer for more details. MR Pin Response WDO Output The TPS3436-Q1 device offers WDO output pin. WDO output is asserted when MR pin voltage is lower than 0.3 X VDD or watchdog timer error is detected. The output will be asserted for tWDO time when any relevant events described above are detected, except for MR event. The time tWDO can be programmed by connecting a capacitor between CRST pin and GND or device will assert tWDO for fixed time duration as selected by orderable part number. Refer section for all available options. describes the relationship between capacitor value and the time tWDO . Ensure the capacitance meets the recommended operating range. Capacitance outside the recommended range can lead to incorrect operation of the device. t WDO (sec) = 4.95 x 106 x CCRST (F) TPS3436-Q1 also offers a unique option of latched output. An orderable with latched output will hold the output in asserted state indefinitely until the device is power cycled or the error condition is addressed. If the output is latched due to MR pin low voltage, the output latch will be released when MR pin voltage rises above 0.7 x VDD level. If the output is latched due to watchdog timer error, the output latch will be released when a WDI negative edge is detected or the device is shutdown and powered up again. shows timing behavior of the device with latched output configuration. Output Latch Timing Behavior Device Functional Modes #GUID-B008A25A-278A-4B38-AFBB-A738DE66DE26/TABLE_UZD_NXV_HVB summarizes the functional modes of the TPS3436-Q1. Device Functional Modes VDD WATCHDOG STATUS WDI WDO VDD < VPOR Not Applicable — Undefined VPOR ≤ VDD < VDDmin Not Applicable Ignored High VDD ≥ VDDmin Disabled Ignored High Enabled tWC(max) ≤ tpulse 1 ≤ tWC(max) + tWO(min) High Enabled tWC(max) > tpulse 1 Low Enabled tWC(max) + tWO(max) < tpulse 1 Low Where tpulse is the time between falling edges on WDI. Detailed Description Overview The TPS3436-Q1 is a high-accuracy window watchdog timer device. The device family supports multiple features related to watchdog operation in a compact 8 pin SOT23 package. The devices are available in 3 different pinout configurations. Each pinout offers access to different features to meet the various application requirements. The device family is rated for -Q100 applications. Overview The TPS3436-Q1 is a high-accuracy window watchdog timer device. The device family supports multiple features related to watchdog operation in a compact 8 pin SOT23 package. The devices are available in 3 different pinout configurations. Each pinout offers access to different features to meet the various application requirements. The device family is rated for -Q100 applications. The TPS3436-Q1 is a high-accuracy window watchdog timer device. The device family supports multiple features related to watchdog operation in a compact 8 pin SOT23 package. The devices are available in 3 different pinout configurations. Each pinout offers access to different features to meet the various application requirements. The device family is rated for -Q100 applications. The TPS3436-Q1 is a high-accuracy window watchdog timer device. The device family supports multiple features related to watchdog operation in a compact 8 pin SOT23 package. The devices are available in 3 different pinout configurations. Each pinout offers access to different features to meet the various application requirements. The device family is rated for -Q100 applications. TPS3436-Q1window 3The device family is rated for -Q100 applications. Functional Block Diagrams Pinout Option A Pinout Option B Pinout Option C Functional Block Diagrams Pinout Option A Pinout Option B Pinout Option C Pinout Option A Pinout Option B Pinout Option C Pinout Option A Pinout Option A Pinout Option B Pinout Option B Pinout Option C Pinout Option C Feature Description Window Watchdog Timer The TPS3436-Q1 offers high precision window watchdog timer monitoring. The device is available in multiple pinout options A to C which support multiple features to meet ever expanding needs of various applications. Ensure a correct pinout is selected to meet the application needs. The window watchdog is active when the VDD voltage is higher than the VDDMIN, MR voltage is held higher than 0.7 x VDD and watchdog is enabled. TPS3436-Q1 family offers various startup time delay options to ensure enough time is available for the host to complete boot operation. Please refer section for additional details. The window watchdog timer frame consists of two windows namely close window (tWC) followed by open window (tWO). The device monitors the WDI pin for falling edge. User is expected to provide a valid falling edge on WDI pin in the open window. Refer to arrive at the relevant close window and open window values needed for application. The timer value is reset when a valid falling edge is detected on WDI pin in the tWO time duration. An early fault is reported if a WDI falling edge is detected in close window. A late fault is reported if WDI falling edge is not detected in both close and open window. The device asserts WDO output for time tWDO in event of watchdog fault. Refer to arrive at the relevant tWDO value needed for application. shows the basic operation for window watchdog timer operation. The TPS3436-Q1 watchdog functionality supports multiple features. Details are available in following sub sections. Window Watchdog Timer Operation tWC (Close Window) Timer The window watchdog frame consists of two sub frames tWC followed by tWO. The host is not expected to drive valid WDI transition during tWC time. A valid WDI transition during tWC frame results in early fault condition and the WDO output is asserted. The tWC timer for TPS3436-Q1 can be set using an external capacitor connected between CWD pin and GND pin. This feature is available with pinout options A or B. Applications which are space constrained or need timer values which meet offered timer options, can benefit when using pinout option C. The TPS3436-Q1 offers multiple fixed timer options ranging from 1 msec up-to 100 sec. The TPS3436-Q1 when using capacitance based timer, senses the capacitance value during the power up. The capacitor is charged and discharged with known internal current source for one cycle to sense the capacitance value. The sensed value is used to arrive at tWC timer for the watchdog operation. This unique implementation helps reduce the continuous charge and discharge current for the capacitor, thus reducing overall current consumption. Continuous charge and discharge of capacitance creates wider dead time (no watchdog monitor functionality) when capacitor is discharging. The dead time is higher for high value of capacitance. The unique implementation of TPS3436-Q1 helps avoid the dead time as the capacitance is not continuously charging or discharging under normal operation. Ensure CCWD is < 200 x CCRST for accurate calibration of capacitance. The close time window is decided based on SETx pin combination and the CWD capacitance. #GUID-D3B3A4B6-F3FF-43A2-9270-9617951C20C1/TABLE_EPC_QP1_DVB to #GUID-D3B3A4B6-F3FF-43A2-9270-9617951C20C1/TABLE_MHQ_NQ1_DVB highlights the relationship between tWC in second and CWD capacitance in farad. The tWC timer is 20% accurate for an ideal capacitor. Accuracy of the capacitance will have additional impact on the tWC time. Ensure the capacitance meets the recommended operating range. Capacitance outside the recommended range can lead to incorrect operation of the device. tWC Equation 1 SET Pin (Pin Configuration A) SET PIN VALUE EQUATION 0 tWC (sec) = 79.2 x 106 x CCWD (F) 1 tWC (sec) = 39.6 x 106 x CCWD (F) tWC Equation 2 SET Pin, WD-EN Not Available (Pin Configuration B) SET PIN VALUE EQUATION 00 tWC (sec) = 79.2 x 106 x CCWD (F) 01 Watchdog disabled 10 tWC (sec) = 39.6 x 106 x CCWD (F) 11 tWC (sec) = 9.9 x 106 x CCWD (F) The TPS3436-Q1 also offers wide selection of high accuracy fixed tWC timer options starting from 1 msec to 100 sec including various industry standard values. The TPS3436-Q1 fixed time options are ±10% accurate for tWC ≥ 10 msec. For tWC < 10 msec, the accuracy is ±20%. tWC value relevant to application can be identified from the orderable part number. Refer to identify mapping of orderable part number to tWC value. tWO (Open Window) Timer The window watchdog frame consists of two sub frames tWC followed by tWO. The host is expected to drive valid WDI transition during tWO time. A valid WDI transition before beginning of tWO frame causes early fault condition. Failure to offer valid WDI transition during tWC and tWO frames results in late fault condition. When a fault condition is detected the WDO output is asserted. The tWO value is derived using tWC value and the window open time ratio value n. Equation highlights the relationship between tWO and tWC. Refer to select available ratio options. tWO = (n - 1) x tWC Each orderable can offer up to 3 ratio options based on the available SET pins. Refer to identify mapping of ratio value to SET pin control. The maximum tWO value is limited to 640 second. Ensure selected tWC and ratio combination does not lead to tWO value greater than 640 second. Watchdog Enable Disable Operation The TPS3436-Q1 supports watchdog enable or disable functionality. This functionality is critical for different use cases as listed below. Disable watchdog during firmware update to avoid host RESET. Disable watchdog during software step-by-step debug operation. Disable watchdog when performing critical task to avoid watchdog error interrupt. Keep watchdog disabled until host boots up. The TPS3436-Q1 supports watchdog enable or disable functionality through either WD-EN pin (pin configuration C) or SET[1:0] = 0b'01 (pin configuration B) logic combination. For a given pinout only one of these two methods is available for the user to disable watchdog operation. For a pinout which offers a WD-EN pin, the watchdog enable disable functionality is controlled by the logic state of WD-EN pin. Drive WD-EN = 1 to enable the watchdog operation or drive WD-EN = 0 to disable the watchdog operation. The WD-EN pin can be toggled any time during the device operation. The diagram shows timing behavior with WD-EN pin control. Watchdog Enable: WD-EN Pin Control SET[1:0] = 0b'01 combination can be used to disable watchdog operation with a pinout which offers SET1 and SET0 pins, but does not include WD-EN pin. The SET pin logic states can be changed at any time during watchdog operation. Refer section for additional details regarding SET[1:0] pin behavior. Pinout options A, B offer watchdog timer control using a capacitance connected between CWD and GND pin. A capacitance value higher than recommended or connect to GND leads to watchdog functionality getting disabled. Capacitance based disable operation overrides the other two options mentioned above. Changing capacitance on the fly does not enable or disable watchdog operation. A power supply recycle is needed to detect change in capacitance. Ongoing watchdog frame is terminated when watchdog is disabled. WDO stays deasserted when watchdog operation is disabled. When enabled the device immediately enters tWC frame and start watchdog monitoring operation. tSD Watchdog Start Up Delay The TPS3436-Q1 supports watchdog startup delay feature. This feature is activated after power up or after WDO assert event. When tSD frame is active, the device monitors the WDI pin but the WDO output is not asserted. This feature allows time for the host complete boot process before watchdog monitoring can take over. The start up delay helps avoid unexpected WDO assert events during boot. The tSD time is predetermined based on the device part number selected. Refer section for details to map the part number to tSD time. Pinout option A, B are available only in no delay or 10 sec start up delay options. The tSD frame is complete when the time duration selected for tSD is over or host provides a valid transition on the WDI pin. The host must provide a valid transition on the WDI pin during tSD time. The device exits the tSD frame and enters watchdog monitoring phase after valid WDI transition. Failure to provide valid transition on WDI pin triggers the watchdog error by asserting the WDO output pin. The tSD frame is not initiated when the watchdog functionality is enabled using WD-EN pin or SET[1:0] pin combination as described in section. shows the operation for tSD time frame. tSD Frame Behavior SET Pin Behavior The TPS3436-Q1 offers one or two SET pins based on the pinout option selected. SET pins offer flexibility to the user to program the tWO timer on the fly to meet various application requirements. Typical use cases where SET pin can be used are Use wide open window timer when host is in sleep mode, change to small timeout operation when host is operational. Watchdog can be used to wake up the host after long duration to perform the application related activities before going back to sleep. Change to wide open window timer when performing system critical tasks to ensure watchdog does not interrupt the critical task. Change timer to application specified interval after the critical task is complete. The tWO timer value for the device is combination of tWC timer selection based on the CWD pin or fixed timer value along with SET pin logic level. The tWC timer value is decided based on the Watchdog Close Time selector in the section. The SET pin logic level is decoded during the device power up. The SET pin value can be changed any time during the operation. SETx pin change which leads to change of watchdog timer value or enable disable state, terminates the ongoing watchdog frame immediately. SETx pins can be updated when WDO output is asserted as well. The updated tWO timer value will be applied after output is deasserted and the tSD timer is over or terminated. For a pinout which offers only SET0 pin to the user, the tWO ratio value is decided based on the Watchdog Open Time Ratio selector field in the orderable part number. Refer for available options. showcases an example of the tWO values for different SET0 logic levels when using Watchdog Close Time setting as option D = 10 msec. tWO Values with SET0 Pin Only (Pin Configuration A) Watchdog Open Time Ratio Selection tWO SET0 = 0 SET0 = 1 A 10 msec 30 msec B 30 msec 70 msec C 70 msec 150 msec D 150 msec 310 msec E 310 msec 630 msec F 630 msec 1270 msec Pinout which offer both SET0 & SET1 pins to the user, the tWO ratio value is decided based on the Watchdog Open Time Ratio selector field in the orderable part number. Refer for available options. Two SETx pins offer 3 different time scaling options. The SET[1:0] = 0b'01 combination disables the watchdog operation. showcases an example of the tWO values for different SET[1:0] logic levels when using Watchdog Close Time setting as option G = 100 msec. The package pin out selected does not offer WD-EN pin. tWO Values with SET0 & SET1 Pins, WD-EN Pin Not Available (Pin Configuration B) Watchdog Open Time Ratio selection tWO SET[1:0] = 0b'00 SET[1:0] = 0b'01 SET[1:0] = 0b'10 SET[1:0] = 0b'11 A 100 msec Watchdog disable 300 msec 1500 msec B 300 msec Watchdog disable 700 msec 3100 msec C 700 msec Watchdog disable 1500 msec 6300 msec D 1500 msec Watchdog disable 3100 msec 12700 msec E 3100 msec Watchdog disable 6300 msec 25500 msec F 6300 msec Watchdog disable 12700 msec 51100 msec Example for Watchdog Close Time setting = 100 msec. Selected pinout option can offer WD-EN pin along with SET[1:0] pins (Pin Configuration C). With this pinout, the WD-EN pin controls watchdog enable and disable operation. The SET[1:0] = 0b'01 combination operates as SET[1:0] = 0b'00. Ensure the tWO value with SETx ratio does not exceed 640 sec. If a selection of close window timer and ratio results in tWO > 640 sec, the timer value will be restricted to 640 sec. to show the timing behavior with respect to SETx status changes. Watchdog Behavior with SETx Pin Status Watchdog Operation with 2 SET Pins Watchdog Operation with 1 SET Pin Manual RESET The TPS3436-Q1 supports manual reset functionality using MR pin. MR pin when driven with voltage lower than 0.3 x VDD, asserts the WDO output. The MR pin has 100 kΩ pull up to VDD. The MR pin can be left floating. The internal pull up makes sure the output is not asserted due to MR pin trigger. The output is deasserted after MR pin voltage rises above 0.7 x VDD voltage. Refer for more details. MR Pin Response WDO Output The TPS3436-Q1 device offers WDO output pin. WDO output is asserted when MR pin voltage is lower than 0.3 X VDD or watchdog timer error is detected. The output will be asserted for tWDO time when any relevant events described above are detected, except for MR event. The time tWDO can be programmed by connecting a capacitor between CRST pin and GND or device will assert tWDO for fixed time duration as selected by orderable part number. Refer section for all available options. describes the relationship between capacitor value and the time tWDO . Ensure the capacitance meets the recommended operating range. Capacitance outside the recommended range can lead to incorrect operation of the device. t WDO (sec) = 4.95 x 106 x CCRST (F) TPS3436-Q1 also offers a unique option of latched output. An orderable with latched output will hold the output in asserted state indefinitely until the device is power cycled or the error condition is addressed. If the output is latched due to MR pin low voltage, the output latch will be released when MR pin voltage rises above 0.7 x VDD level. If the output is latched due to watchdog timer error, the output latch will be released when a WDI negative edge is detected or the device is shutdown and powered up again. shows timing behavior of the device with latched output configuration. Output Latch Timing Behavior Feature Description Window Watchdog Timer The TPS3436-Q1 offers high precision window watchdog timer monitoring. The device is available in multiple pinout options A to C which support multiple features to meet ever expanding needs of various applications. Ensure a correct pinout is selected to meet the application needs. The window watchdog is active when the VDD voltage is higher than the VDDMIN, MR voltage is held higher than 0.7 x VDD and watchdog is enabled. TPS3436-Q1 family offers various startup time delay options to ensure enough time is available for the host to complete boot operation. Please refer section for additional details. The window watchdog timer frame consists of two windows namely close window (tWC) followed by open window (tWO). The device monitors the WDI pin for falling edge. User is expected to provide a valid falling edge on WDI pin in the open window. Refer to arrive at the relevant close window and open window values needed for application. The timer value is reset when a valid falling edge is detected on WDI pin in the tWO time duration. An early fault is reported if a WDI falling edge is detected in close window. A late fault is reported if WDI falling edge is not detected in both close and open window. The device asserts WDO output for time tWDO in event of watchdog fault. Refer to arrive at the relevant tWDO value needed for application. shows the basic operation for window watchdog timer operation. The TPS3436-Q1 watchdog functionality supports multiple features. Details are available in following sub sections. Window Watchdog Timer Operation tWC (Close Window) Timer The window watchdog frame consists of two sub frames tWC followed by tWO. The host is not expected to drive valid WDI transition during tWC time. A valid WDI transition during tWC frame results in early fault condition and the WDO output is asserted. The tWC timer for TPS3436-Q1 can be set using an external capacitor connected between CWD pin and GND pin. This feature is available with pinout options A or B. Applications which are space constrained or need timer values which meet offered timer options, can benefit when using pinout option C. The TPS3436-Q1 offers multiple fixed timer options ranging from 1 msec up-to 100 sec. The TPS3436-Q1 when using capacitance based timer, senses the capacitance value during the power up. The capacitor is charged and discharged with known internal current source for one cycle to sense the capacitance value. The sensed value is used to arrive at tWC timer for the watchdog operation. This unique implementation helps reduce the continuous charge and discharge current for the capacitor, thus reducing overall current consumption. Continuous charge and discharge of capacitance creates wider dead time (no watchdog monitor functionality) when capacitor is discharging. The dead time is higher for high value of capacitance. The unique implementation of TPS3436-Q1 helps avoid the dead time as the capacitance is not continuously charging or discharging under normal operation. Ensure CCWD is < 200 x CCRST for accurate calibration of capacitance. The close time window is decided based on SETx pin combination and the CWD capacitance. #GUID-D3B3A4B6-F3FF-43A2-9270-9617951C20C1/TABLE_EPC_QP1_DVB to #GUID-D3B3A4B6-F3FF-43A2-9270-9617951C20C1/TABLE_MHQ_NQ1_DVB highlights the relationship between tWC in second and CWD capacitance in farad. The tWC timer is 20% accurate for an ideal capacitor. Accuracy of the capacitance will have additional impact on the tWC time. Ensure the capacitance meets the recommended operating range. Capacitance outside the recommended range can lead to incorrect operation of the device. tWC Equation 1 SET Pin (Pin Configuration A) SET PIN VALUE EQUATION 0 tWC (sec) = 79.2 x 106 x CCWD (F) 1 tWC (sec) = 39.6 x 106 x CCWD (F) tWC Equation 2 SET Pin, WD-EN Not Available (Pin Configuration B) SET PIN VALUE EQUATION 00 tWC (sec) = 79.2 x 106 x CCWD (F) 01 Watchdog disabled 10 tWC (sec) = 39.6 x 106 x CCWD (F) 11 tWC (sec) = 9.9 x 106 x CCWD (F) The TPS3436-Q1 also offers wide selection of high accuracy fixed tWC timer options starting from 1 msec to 100 sec including various industry standard values. The TPS3436-Q1 fixed time options are ±10% accurate for tWC ≥ 10 msec. For tWC < 10 msec, the accuracy is ±20%. tWC value relevant to application can be identified from the orderable part number. Refer to identify mapping of orderable part number to tWC value. tWO (Open Window) Timer The window watchdog frame consists of two sub frames tWC followed by tWO. The host is expected to drive valid WDI transition during tWO time. A valid WDI transition before beginning of tWO frame causes early fault condition. Failure to offer valid WDI transition during tWC and tWO frames results in late fault condition. When a fault condition is detected the WDO output is asserted. The tWO value is derived using tWC value and the window open time ratio value n. Equation highlights the relationship between tWO and tWC. Refer to select available ratio options. tWO = (n - 1) x tWC Each orderable can offer up to 3 ratio options based on the available SET pins. Refer to identify mapping of ratio value to SET pin control. The maximum tWO value is limited to 640 second. Ensure selected tWC and ratio combination does not lead to tWO value greater than 640 second. Watchdog Enable Disable Operation The TPS3436-Q1 supports watchdog enable or disable functionality. This functionality is critical for different use cases as listed below. Disable watchdog during firmware update to avoid host RESET. Disable watchdog during software step-by-step debug operation. Disable watchdog when performing critical task to avoid watchdog error interrupt. Keep watchdog disabled until host boots up. The TPS3436-Q1 supports watchdog enable or disable functionality through either WD-EN pin (pin configuration C) or SET[1:0] = 0b'01 (pin configuration B) logic combination. For a given pinout only one of these two methods is available for the user to disable watchdog operation. For a pinout which offers a WD-EN pin, the watchdog enable disable functionality is controlled by the logic state of WD-EN pin. Drive WD-EN = 1 to enable the watchdog operation or drive WD-EN = 0 to disable the watchdog operation. The WD-EN pin can be toggled any time during the device operation. The diagram shows timing behavior with WD-EN pin control. Watchdog Enable: WD-EN Pin Control SET[1:0] = 0b'01 combination can be used to disable watchdog operation with a pinout which offers SET1 and SET0 pins, but does not include WD-EN pin. The SET pin logic states can be changed at any time during watchdog operation. Refer section for additional details regarding SET[1:0] pin behavior. Pinout options A, B offer watchdog timer control using a capacitance connected between CWD and GND pin. A capacitance value higher than recommended or connect to GND leads to watchdog functionality getting disabled. Capacitance based disable operation overrides the other two options mentioned above. Changing capacitance on the fly does not enable or disable watchdog operation. A power supply recycle is needed to detect change in capacitance. Ongoing watchdog frame is terminated when watchdog is disabled. WDO stays deasserted when watchdog operation is disabled. When enabled the device immediately enters tWC frame and start watchdog monitoring operation. tSD Watchdog Start Up Delay The TPS3436-Q1 supports watchdog startup delay feature. This feature is activated after power up or after WDO assert event. When tSD frame is active, the device monitors the WDI pin but the WDO output is not asserted. This feature allows time for the host complete boot process before watchdog monitoring can take over. The start up delay helps avoid unexpected WDO assert events during boot. The tSD time is predetermined based on the device part number selected. Refer section for details to map the part number to tSD time. Pinout option A, B are available only in no delay or 10 sec start up delay options. The tSD frame is complete when the time duration selected for tSD is over or host provides a valid transition on the WDI pin. The host must provide a valid transition on the WDI pin during tSD time. The device exits the tSD frame and enters watchdog monitoring phase after valid WDI transition. Failure to provide valid transition on WDI pin triggers the watchdog error by asserting the WDO output pin. The tSD frame is not initiated when the watchdog functionality is enabled using WD-EN pin or SET[1:0] pin combination as described in section. shows the operation for tSD time frame. tSD Frame Behavior SET Pin Behavior The TPS3436-Q1 offers one or two SET pins based on the pinout option selected. SET pins offer flexibility to the user to program the tWO timer on the fly to meet various application requirements. Typical use cases where SET pin can be used are Use wide open window timer when host is in sleep mode, change to small timeout operation when host is operational. Watchdog can be used to wake up the host after long duration to perform the application related activities before going back to sleep. Change to wide open window timer when performing system critical tasks to ensure watchdog does not interrupt the critical task. Change timer to application specified interval after the critical task is complete. The tWO timer value for the device is combination of tWC timer selection based on the CWD pin or fixed timer value along with SET pin logic level. The tWC timer value is decided based on the Watchdog Close Time selector in the section. The SET pin logic level is decoded during the device power up. The SET pin value can be changed any time during the operation. SETx pin change which leads to change of watchdog timer value or enable disable state, terminates the ongoing watchdog frame immediately. SETx pins can be updated when WDO output is asserted as well. The updated tWO timer value will be applied after output is deasserted and the tSD timer is over or terminated. For a pinout which offers only SET0 pin to the user, the tWO ratio value is decided based on the Watchdog Open Time Ratio selector field in the orderable part number. Refer for available options. showcases an example of the tWO values for different SET0 logic levels when using Watchdog Close Time setting as option D = 10 msec. tWO Values with SET0 Pin Only (Pin Configuration A) Watchdog Open Time Ratio Selection tWO SET0 = 0 SET0 = 1 A 10 msec 30 msec B 30 msec 70 msec C 70 msec 150 msec D 150 msec 310 msec E 310 msec 630 msec F 630 msec 1270 msec Pinout which offer both SET0 & SET1 pins to the user, the tWO ratio value is decided based on the Watchdog Open Time Ratio selector field in the orderable part number. Refer for available options. Two SETx pins offer 3 different time scaling options. The SET[1:0] = 0b'01 combination disables the watchdog operation. showcases an example of the tWO values for different SET[1:0] logic levels when using Watchdog Close Time setting as option G = 100 msec. The package pin out selected does not offer WD-EN pin. tWO Values with SET0 & SET1 Pins, WD-EN Pin Not Available (Pin Configuration B) Watchdog Open Time Ratio selection tWO SET[1:0] = 0b'00 SET[1:0] = 0b'01 SET[1:0] = 0b'10 SET[1:0] = 0b'11 A 100 msec Watchdog disable 300 msec 1500 msec B 300 msec Watchdog disable 700 msec 3100 msec C 700 msec Watchdog disable 1500 msec 6300 msec D 1500 msec Watchdog disable 3100 msec 12700 msec E 3100 msec Watchdog disable 6300 msec 25500 msec F 6300 msec Watchdog disable 12700 msec 51100 msec Example for Watchdog Close Time setting = 100 msec. Selected pinout option can offer WD-EN pin along with SET[1:0] pins (Pin Configuration C). With this pinout, the WD-EN pin controls watchdog enable and disable operation. The SET[1:0] = 0b'01 combination operates as SET[1:0] = 0b'00. Ensure the tWO value with SETx ratio does not exceed 640 sec. If a selection of close window timer and ratio results in tWO > 640 sec, the timer value will be restricted to 640 sec. to show the timing behavior with respect to SETx status changes. Watchdog Behavior with SETx Pin Status Watchdog Operation with 2 SET Pins Watchdog Operation with 1 SET Pin Window Watchdog Timer The TPS3436-Q1 offers high precision window watchdog timer monitoring. The device is available in multiple pinout options A to C which support multiple features to meet ever expanding needs of various applications. Ensure a correct pinout is selected to meet the application needs. The window watchdog is active when the VDD voltage is higher than the VDDMIN, MR voltage is held higher than 0.7 x VDD and watchdog is enabled. TPS3436-Q1 family offers various startup time delay options to ensure enough time is available for the host to complete boot operation. Please refer section for additional details. The window watchdog timer frame consists of two windows namely close window (tWC) followed by open window (tWO). The device monitors the WDI pin for falling edge. User is expected to provide a valid falling edge on WDI pin in the open window. Refer to arrive at the relevant close window and open window values needed for application. The timer value is reset when a valid falling edge is detected on WDI pin in the tWO time duration. An early fault is reported if a WDI falling edge is detected in close window. A late fault is reported if WDI falling edge is not detected in both close and open window. The device asserts WDO output for time tWDO in event of watchdog fault. Refer to arrive at the relevant tWDO value needed for application. shows the basic operation for window watchdog timer operation. The TPS3436-Q1 watchdog functionality supports multiple features. Details are available in following sub sections. Window Watchdog Timer Operation The TPS3436-Q1 offers high precision window watchdog timer monitoring. The device is available in multiple pinout options A to C which support multiple features to meet ever expanding needs of various applications. Ensure a correct pinout is selected to meet the application needs. The window watchdog is active when the VDD voltage is higher than the VDDMIN, MR voltage is held higher than 0.7 x VDD and watchdog is enabled. TPS3436-Q1 family offers various startup time delay options to ensure enough time is available for the host to complete boot operation. Please refer section for additional details. The window watchdog timer frame consists of two windows namely close window (tWC) followed by open window (tWO). The device monitors the WDI pin for falling edge. User is expected to provide a valid falling edge on WDI pin in the open window. Refer to arrive at the relevant close window and open window values needed for application. The timer value is reset when a valid falling edge is detected on WDI pin in the tWO time duration. An early fault is reported if a WDI falling edge is detected in close window. A late fault is reported if WDI falling edge is not detected in both close and open window. The device asserts WDO output for time tWDO in event of watchdog fault. Refer to arrive at the relevant tWDO value needed for application. shows the basic operation for window watchdog timer operation. The TPS3436-Q1 watchdog functionality supports multiple features. Details are available in following sub sections. Window Watchdog Timer Operation The TPS3436-Q1 offers high precision window watchdog timer monitoring. The device is available in multiple pinout options A to C which support multiple features to meet ever expanding needs of various applications. Ensure a correct pinout is selected to meet the application needs.TPS3436-Q1C The window watchdog is active when the VDD voltage is higher than the VDDMIN, MR voltage is held higher than 0.7 x VDD and watchdog is enabled. TPS3436-Q1 family offers various startup time delay options to ensure enough time is available for the host to complete boot operation. Please refer section for additional details.The window watchdog is active when the VDD voltage is higher than the VDDMIN, MR voltage is held higher than 0.7 x VDD and watchdog is enabled.MINMRTPS3436-Q1 The window watchdog timer frame consists of two windows namely close window (tWC) followed by open window (tWO). The device monitors the WDI pin for falling edge. User is expected to provide a valid falling edge on WDI pin in the open window. Refer to arrive at the relevant close window and open window values needed for application. The timer value is reset when a valid falling edge is detected on WDI pin in the tWO time duration. An early fault is reported if a WDI falling edge is detected in close window. A late fault is reported if WDI falling edge is not detected in both close and open window. The device asserts WDO output for time tWDO in event of watchdog fault. Refer to arrive at the relevant tWDO value needed for application.WCWO WOThe device asserts WDO outputtWDO WDO tWDO WDO shows the basic operation for window watchdog timer operation. The TPS3436-Q1 watchdog functionality supports multiple features. Details are available in following sub sections.TPS3436-Q1 Window Watchdog Timer Operation Window Watchdog Timer Operation tWC (Close Window) Timer The window watchdog frame consists of two sub frames tWC followed by tWO. The host is not expected to drive valid WDI transition during tWC time. A valid WDI transition during tWC frame results in early fault condition and the WDO output is asserted. The tWC timer for TPS3436-Q1 can be set using an external capacitor connected between CWD pin and GND pin. This feature is available with pinout options A or B. Applications which are space constrained or need timer values which meet offered timer options, can benefit when using pinout option C. The TPS3436-Q1 offers multiple fixed timer options ranging from 1 msec up-to 100 sec. The TPS3436-Q1 when using capacitance based timer, senses the capacitance value during the power up. The capacitor is charged and discharged with known internal current source for one cycle to sense the capacitance value. The sensed value is used to arrive at tWC timer for the watchdog operation. This unique implementation helps reduce the continuous charge and discharge current for the capacitor, thus reducing overall current consumption. Continuous charge and discharge of capacitance creates wider dead time (no watchdog monitor functionality) when capacitor is discharging. The dead time is higher for high value of capacitance. The unique implementation of TPS3436-Q1 helps avoid the dead time as the capacitance is not continuously charging or discharging under normal operation. Ensure CCWD is < 200 x CCRST for accurate calibration of capacitance. The close time window is decided based on SETx pin combination and the CWD capacitance. #GUID-D3B3A4B6-F3FF-43A2-9270-9617951C20C1/TABLE_EPC_QP1_DVB to #GUID-D3B3A4B6-F3FF-43A2-9270-9617951C20C1/TABLE_MHQ_NQ1_DVB highlights the relationship between tWC in second and CWD capacitance in farad. The tWC timer is 20% accurate for an ideal capacitor. Accuracy of the capacitance will have additional impact on the tWC time. Ensure the capacitance meets the recommended operating range. Capacitance outside the recommended range can lead to incorrect operation of the device. tWC Equation 1 SET Pin (Pin Configuration A) SET PIN VALUE EQUATION 0 tWC (sec) = 79.2 x 106 x CCWD (F) 1 tWC (sec) = 39.6 x 106 x CCWD (F) tWC Equation 2 SET Pin, WD-EN Not Available (Pin Configuration B) SET PIN VALUE EQUATION 00 tWC (sec) = 79.2 x 106 x CCWD (F) 01 Watchdog disabled 10 tWC (sec) = 39.6 x 106 x CCWD (F) 11 tWC (sec) = 9.9 x 106 x CCWD (F) The TPS3436-Q1 also offers wide selection of high accuracy fixed tWC timer options starting from 1 msec to 100 sec including various industry standard values. The TPS3436-Q1 fixed time options are ±10% accurate for tWC ≥ 10 msec. For tWC < 10 msec, the accuracy is ±20%. tWC value relevant to application can be identified from the orderable part number. Refer to identify mapping of orderable part number to tWC value. tWC (Close Window) TimerWC The window watchdog frame consists of two sub frames tWC followed by tWO. The host is not expected to drive valid WDI transition during tWC time. A valid WDI transition during tWC frame results in early fault condition and the WDO output is asserted. The tWC timer for TPS3436-Q1 can be set using an external capacitor connected between CWD pin and GND pin. This feature is available with pinout options A or B. Applications which are space constrained or need timer values which meet offered timer options, can benefit when using pinout option C. The TPS3436-Q1 offers multiple fixed timer options ranging from 1 msec up-to 100 sec. The TPS3436-Q1 when using capacitance based timer, senses the capacitance value during the power up. The capacitor is charged and discharged with known internal current source for one cycle to sense the capacitance value. The sensed value is used to arrive at tWC timer for the watchdog operation. This unique implementation helps reduce the continuous charge and discharge current for the capacitor, thus reducing overall current consumption. Continuous charge and discharge of capacitance creates wider dead time (no watchdog monitor functionality) when capacitor is discharging. The dead time is higher for high value of capacitance. The unique implementation of TPS3436-Q1 helps avoid the dead time as the capacitance is not continuously charging or discharging under normal operation. Ensure CCWD is < 200 x CCRST for accurate calibration of capacitance. The close time window is decided based on SETx pin combination and the CWD capacitance. #GUID-D3B3A4B6-F3FF-43A2-9270-9617951C20C1/TABLE_EPC_QP1_DVB to #GUID-D3B3A4B6-F3FF-43A2-9270-9617951C20C1/TABLE_MHQ_NQ1_DVB highlights the relationship between tWC in second and CWD capacitance in farad. The tWC timer is 20% accurate for an ideal capacitor. Accuracy of the capacitance will have additional impact on the tWC time. Ensure the capacitance meets the recommended operating range. Capacitance outside the recommended range can lead to incorrect operation of the device. tWC Equation 1 SET Pin (Pin Configuration A) SET PIN VALUE EQUATION 0 tWC (sec) = 79.2 x 106 x CCWD (F) 1 tWC (sec) = 39.6 x 106 x CCWD (F) tWC Equation 2 SET Pin, WD-EN Not Available (Pin Configuration B) SET PIN VALUE EQUATION 00 tWC (sec) = 79.2 x 106 x CCWD (F) 01 Watchdog disabled 10 tWC (sec) = 39.6 x 106 x CCWD (F) 11 tWC (sec) = 9.9 x 106 x CCWD (F) The TPS3436-Q1 also offers wide selection of high accuracy fixed tWC timer options starting from 1 msec to 100 sec including various industry standard values. The TPS3436-Q1 fixed time options are ±10% accurate for tWC ≥ 10 msec. For tWC < 10 msec, the accuracy is ±20%. tWC value relevant to application can be identified from the orderable part number. Refer to identify mapping of orderable part number to tWC value. The window watchdog frame consists of two sub frames tWC followed by tWO. The host is not expected to drive valid WDI transition during tWC time. A valid WDI transition during tWC frame results in early fault condition and the WDO output is asserted. The tWC timer for TPS3436-Q1 can be set using an external capacitor connected between CWD pin and GND pin. This feature is available with pinout options A or B. Applications which are space constrained or need timer values which meet offered timer options, can benefit when using pinout option C. The TPS3436-Q1 offers multiple fixed timer options ranging from 1 msec up-to 100 sec. The TPS3436-Q1 when using capacitance based timer, senses the capacitance value during the power up. The capacitor is charged and discharged with known internal current source for one cycle to sense the capacitance value. The sensed value is used to arrive at tWC timer for the watchdog operation. This unique implementation helps reduce the continuous charge and discharge current for the capacitor, thus reducing overall current consumption. Continuous charge and discharge of capacitance creates wider dead time (no watchdog monitor functionality) when capacitor is discharging. The dead time is higher for high value of capacitance. The unique implementation of TPS3436-Q1 helps avoid the dead time as the capacitance is not continuously charging or discharging under normal operation. Ensure CCWD is < 200 x CCRST for accurate calibration of capacitance. The close time window is decided based on SETx pin combination and the CWD capacitance. #GUID-D3B3A4B6-F3FF-43A2-9270-9617951C20C1/TABLE_EPC_QP1_DVB to #GUID-D3B3A4B6-F3FF-43A2-9270-9617951C20C1/TABLE_MHQ_NQ1_DVB highlights the relationship between tWC in second and CWD capacitance in farad. The tWC timer is 20% accurate for an ideal capacitor. Accuracy of the capacitance will have additional impact on the tWC time. Ensure the capacitance meets the recommended operating range. Capacitance outside the recommended range can lead to incorrect operation of the device. tWC Equation 1 SET Pin (Pin Configuration A) SET PIN VALUE EQUATION 0 tWC (sec) = 79.2 x 106 x CCWD (F) 1 tWC (sec) = 39.6 x 106 x CCWD (F) tWC Equation 2 SET Pin, WD-EN Not Available (Pin Configuration B) SET PIN VALUE EQUATION 00 tWC (sec) = 79.2 x 106 x CCWD (F) 01 Watchdog disabled 10 tWC (sec) = 39.6 x 106 x CCWD (F) 11 tWC (sec) = 9.9 x 106 x CCWD (F) The TPS3436-Q1 also offers wide selection of high accuracy fixed tWC timer options starting from 1 msec to 100 sec including various industry standard values. The TPS3436-Q1 fixed time options are ±10% accurate for tWC ≥ 10 msec. For tWC < 10 msec, the accuracy is ±20%. tWC value relevant to application can be identified from the orderable part number. Refer to identify mapping of orderable part number to tWC value. The window watchdog frame consists of two sub frames tWC followed by tWO. The host is not expected to drive valid WDI transition during tWC time. A valid WDI transition during tWC frame results in early fault condition and the WDO output is asserted. The tWC timer for TPS3436-Q1 can be set using an external capacitor connected between CWD pin and GND pin. This feature is available with pinout options A or B. Applications which are space constrained or need timer values which meet offered timer options, can benefit when using pinout option C. The TPS3436-Q1 offers multiple fixed timer options ranging from 1 msec up-to 100 sec.WCWOWCWCWCTPS3436-Q1TPS3436-Q1The TPS3436-Q1 when using capacitance based timer, senses the capacitance value during the power up. The capacitor is charged and discharged with known internal current source for one cycle to sense the capacitance value. The sensed value is used to arrive at tWC timer for the watchdog operation. This unique implementation helps reduce the continuous charge and discharge current for the capacitor, thus reducing overall current consumption. Continuous charge and discharge of capacitance creates wider dead time (no watchdog monitor functionality) when capacitor is discharging. The dead time is higher for high value of capacitance. The unique implementation of TPS3436-Q1 helps avoid the dead time as the capacitance is not continuously charging or discharging under normal operation. Ensure CCWD is < 200 x CCRST for accurate calibration of capacitance. The close time window is decided based on SETx pin combination and the CWD capacitance. #GUID-D3B3A4B6-F3FF-43A2-9270-9617951C20C1/TABLE_EPC_QP1_DVB to #GUID-D3B3A4B6-F3FF-43A2-9270-9617951C20C1/TABLE_MHQ_NQ1_DVB highlights the relationship between tWC in second and CWD capacitance in farad. The tWC timer is 20% accurate for an ideal capacitor. Accuracy of the capacitance will have additional impact on the tWC time. Ensure the capacitance meets the recommended operating range. Capacitance outside the recommended range can lead to incorrect operation of the device.TPS3436-Q1WCTPS3436-Q1CWDCRST#GUID-D3B3A4B6-F3FF-43A2-9270-9617951C20C1/TABLE_EPC_QP1_DVB#GUID-D3B3A4B6-F3FF-43A2-9270-9617951C20C1/TABLE_MHQ_NQ1_DVBWCWCWC tWC Equation 1 SET Pin (Pin Configuration A) SET PIN VALUE EQUATION 0 tWC (sec) = 79.2 x 106 x CCWD (F) 1 tWC (sec) = 39.6 x 106 x CCWD (F) tWC Equation 1 SET Pin (Pin Configuration A)WC SET PIN VALUE EQUATION 0 tWC (sec) = 79.2 x 106 x CCWD (F) 1 tWC (sec) = 39.6 x 106 x CCWD (F) SET PIN VALUE EQUATION SET PIN VALUE EQUATION SET PIN VALUEEQUATION 0 tWC (sec) = 79.2 x 106 x CCWD (F) 1 tWC (sec) = 39.6 x 106 x CCWD (F) 0 tWC (sec) = 79.2 x 106 x CCWD (F) 0tWC (sec) = 79.2 x 106 x CCWD (F)WC6CWD 1 tWC (sec) = 39.6 x 106 x CCWD (F) 1tWC (sec) = 39.6 x 106 x CCWD (F)WC6CWD tWC Equation 2 SET Pin, WD-EN Not Available (Pin Configuration B) SET PIN VALUE EQUATION 00 tWC (sec) = 79.2 x 106 x CCWD (F) 01 Watchdog disabled 10 tWC (sec) = 39.6 x 106 x CCWD (F) 11 tWC (sec) = 9.9 x 106 x CCWD (F) tWC Equation 2 SET Pin, WD-EN Not Available (Pin Configuration B)WC SET PIN VALUE EQUATION 00 tWC (sec) = 79.2 x 106 x CCWD (F) 01 Watchdog disabled 10 tWC (sec) = 39.6 x 106 x CCWD (F) 11 tWC (sec) = 9.9 x 106 x CCWD (F) SET PIN VALUE EQUATION SET PIN VALUE EQUATION SET PIN VALUEEQUATION 00 tWC (sec) = 79.2 x 106 x CCWD (F) 01 Watchdog disabled 10 tWC (sec) = 39.6 x 106 x CCWD (F) 11 tWC (sec) = 9.9 x 106 x CCWD (F) 00 tWC (sec) = 79.2 x 106 x CCWD (F) 00tWC (sec) = 79.2 x 106 x CCWD (F)WC6CWD 01 Watchdog disabled 01Watchdog disabled 10 tWC (sec) = 39.6 x 106 x CCWD (F) 10tWC (sec) = 39.6 x 106 x CCWD (F)WC6CWD 11 tWC (sec) = 9.9 x 106 x CCWD (F) 11tWC (sec) = 9.9 x 106 x CCWD (F)WC6CWDThe TPS3436-Q1 also offers wide selection of high accuracy fixed tWC timer options starting from 1 msec to 100 sec including various industry standard values. The TPS3436-Q1 fixed time options are ±10% accurate for tWC ≥ 10 msec. For tWC < 10 msec, the accuracy is ±20%. tWC value relevant to application can be identified from the orderable part number. Refer to identify mapping of orderable part number to tWC value.TPS3436-Q1WCTPS3436-Q1WCWCWC WC tWO (Open Window) Timer The window watchdog frame consists of two sub frames tWC followed by tWO. The host is expected to drive valid WDI transition during tWO time. A valid WDI transition before beginning of tWO frame causes early fault condition. Failure to offer valid WDI transition during tWC and tWO frames results in late fault condition. When a fault condition is detected the WDO output is asserted. The tWO value is derived using tWC value and the window open time ratio value n. Equation highlights the relationship between tWO and tWC. Refer to select available ratio options. tWO = (n - 1) x tWC Each orderable can offer up to 3 ratio options based on the available SET pins. Refer to identify mapping of ratio value to SET pin control. The maximum tWO value is limited to 640 second. Ensure selected tWC and ratio combination does not lead to tWO value greater than 640 second. tWO (Open Window) TimerWO The window watchdog frame consists of two sub frames tWC followed by tWO. The host is expected to drive valid WDI transition during tWO time. A valid WDI transition before beginning of tWO frame causes early fault condition. Failure to offer valid WDI transition during tWC and tWO frames results in late fault condition. When a fault condition is detected the WDO output is asserted. The tWO value is derived using tWC value and the window open time ratio value n. Equation highlights the relationship between tWO and tWC. Refer to select available ratio options. tWO = (n - 1) x tWC Each orderable can offer up to 3 ratio options based on the available SET pins. Refer to identify mapping of ratio value to SET pin control. The maximum tWO value is limited to 640 second. Ensure selected tWC and ratio combination does not lead to tWO value greater than 640 second. The window watchdog frame consists of two sub frames tWC followed by tWO. The host is expected to drive valid WDI transition during tWO time. A valid WDI transition before beginning of tWO frame causes early fault condition. Failure to offer valid WDI transition during tWC and tWO frames results in late fault condition. When a fault condition is detected the WDO output is asserted. The tWO value is derived using tWC value and the window open time ratio value n. Equation highlights the relationship between tWO and tWC. Refer to select available ratio options. tWO = (n - 1) x tWC Each orderable can offer up to 3 ratio options based on the available SET pins. Refer to identify mapping of ratio value to SET pin control. The maximum tWO value is limited to 640 second. Ensure selected tWC and ratio combination does not lead to tWO value greater than 640 second. The window watchdog frame consists of two sub frames tWC followed by tWO. The host is expected to drive valid WDI transition during tWO time. A valid WDI transition before beginning of tWO frame causes early fault condition. Failure to offer valid WDI transition during tWC and tWO frames results in late fault condition. When a fault condition is detected the WDO output is asserted. WCWOWOWOWCWOThe tWO value is derived using tWC value and the window open time ratio value n. Equation highlights the relationship between tWO and tWC. Refer to select available ratio options.WOWCnEquationWOWCtWO = (n - 1) x tWC WOnWCEach orderable can offer up to 3 ratio options based on the available SET pins. Refer to identify mapping of ratio value to SET pin control. The maximum tWO value is limited to 640 second. Ensure selected tWC and ratio combination does not lead to tWO value greater than 640 second.WOWCWO Watchdog Enable Disable Operation The TPS3436-Q1 supports watchdog enable or disable functionality. This functionality is critical for different use cases as listed below. Disable watchdog during firmware update to avoid host RESET. Disable watchdog during software step-by-step debug operation. Disable watchdog when performing critical task to avoid watchdog error interrupt. Keep watchdog disabled until host boots up. The TPS3436-Q1 supports watchdog enable or disable functionality through either WD-EN pin (pin configuration C) or SET[1:0] = 0b'01 (pin configuration B) logic combination. For a given pinout only one of these two methods is available for the user to disable watchdog operation. For a pinout which offers a WD-EN pin, the watchdog enable disable functionality is controlled by the logic state of WD-EN pin. Drive WD-EN = 1 to enable the watchdog operation or drive WD-EN = 0 to disable the watchdog operation. The WD-EN pin can be toggled any time during the device operation. The diagram shows timing behavior with WD-EN pin control. Watchdog Enable: WD-EN Pin Control SET[1:0] = 0b'01 combination can be used to disable watchdog operation with a pinout which offers SET1 and SET0 pins, but does not include WD-EN pin. The SET pin logic states can be changed at any time during watchdog operation. Refer section for additional details regarding SET[1:0] pin behavior. Pinout options A, B offer watchdog timer control using a capacitance connected between CWD and GND pin. A capacitance value higher than recommended or connect to GND leads to watchdog functionality getting disabled. Capacitance based disable operation overrides the other two options mentioned above. Changing capacitance on the fly does not enable or disable watchdog operation. A power supply recycle is needed to detect change in capacitance. Ongoing watchdog frame is terminated when watchdog is disabled. WDO stays deasserted when watchdog operation is disabled. When enabled the device immediately enters tWC frame and start watchdog monitoring operation. Watchdog Enable Disable Operation The TPS3436-Q1 supports watchdog enable or disable functionality. This functionality is critical for different use cases as listed below. Disable watchdog during firmware update to avoid host RESET. Disable watchdog during software step-by-step debug operation. Disable watchdog when performing critical task to avoid watchdog error interrupt. Keep watchdog disabled until host boots up. The TPS3436-Q1 supports watchdog enable or disable functionality through either WD-EN pin (pin configuration C) or SET[1:0] = 0b'01 (pin configuration B) logic combination. For a given pinout only one of these two methods is available for the user to disable watchdog operation. For a pinout which offers a WD-EN pin, the watchdog enable disable functionality is controlled by the logic state of WD-EN pin. Drive WD-EN = 1 to enable the watchdog operation or drive WD-EN = 0 to disable the watchdog operation. The WD-EN pin can be toggled any time during the device operation. The diagram shows timing behavior with WD-EN pin control. Watchdog Enable: WD-EN Pin Control SET[1:0] = 0b'01 combination can be used to disable watchdog operation with a pinout which offers SET1 and SET0 pins, but does not include WD-EN pin. The SET pin logic states can be changed at any time during watchdog operation. Refer section for additional details regarding SET[1:0] pin behavior. Pinout options A, B offer watchdog timer control using a capacitance connected between CWD and GND pin. A capacitance value higher than recommended or connect to GND leads to watchdog functionality getting disabled. Capacitance based disable operation overrides the other two options mentioned above. Changing capacitance on the fly does not enable or disable watchdog operation. A power supply recycle is needed to detect change in capacitance. Ongoing watchdog frame is terminated when watchdog is disabled. WDO stays deasserted when watchdog operation is disabled. When enabled the device immediately enters tWC frame and start watchdog monitoring operation. The TPS3436-Q1 supports watchdog enable or disable functionality. This functionality is critical for different use cases as listed below. Disable watchdog during firmware update to avoid host RESET. Disable watchdog during software step-by-step debug operation. Disable watchdog when performing critical task to avoid watchdog error interrupt. Keep watchdog disabled until host boots up. The TPS3436-Q1 supports watchdog enable or disable functionality through either WD-EN pin (pin configuration C) or SET[1:0] = 0b'01 (pin configuration B) logic combination. For a given pinout only one of these two methods is available for the user to disable watchdog operation. For a pinout which offers a WD-EN pin, the watchdog enable disable functionality is controlled by the logic state of WD-EN pin. Drive WD-EN = 1 to enable the watchdog operation or drive WD-EN = 0 to disable the watchdog operation. The WD-EN pin can be toggled any time during the device operation. The diagram shows timing behavior with WD-EN pin control. Watchdog Enable: WD-EN Pin Control SET[1:0] = 0b'01 combination can be used to disable watchdog operation with a pinout which offers SET1 and SET0 pins, but does not include WD-EN pin. The SET pin logic states can be changed at any time during watchdog operation. Refer section for additional details regarding SET[1:0] pin behavior. Pinout options A, B offer watchdog timer control using a capacitance connected between CWD and GND pin. A capacitance value higher than recommended or connect to GND leads to watchdog functionality getting disabled. Capacitance based disable operation overrides the other two options mentioned above. Changing capacitance on the fly does not enable or disable watchdog operation. A power supply recycle is needed to detect change in capacitance. Ongoing watchdog frame is terminated when watchdog is disabled. WDO stays deasserted when watchdog operation is disabled. When enabled the device immediately enters tWC frame and start watchdog monitoring operation. The TPS3436-Q1 supports watchdog enable or disable functionality. This functionality is critical for different use cases as listed below.TPS3436-Q1 Disable watchdog during firmware update to avoid host RESET. Disable watchdog during software step-by-step debug operation. Disable watchdog when performing critical task to avoid watchdog error interrupt. Keep watchdog disabled until host boots up. Disable watchdog during firmware update to avoid host RESET.Disable watchdog during software step-by-step debug operation.Disable watchdog when performing critical task to avoid watchdog error interrupt.Keep watchdog disabled until host boots up.The TPS3436-Q1 supports watchdog enable or disable functionality through either WD-EN pin (pin configuration C) or SET[1:0] = 0b'01 (pin configuration B) logic combination. For a given pinout only one of these two methods is available for the user to disable watchdog operation.TPS3436-Q1For a pinout which offers a WD-EN pin, the watchdog enable disable functionality is controlled by the logic state of WD-EN pin. Drive WD-EN = 1 to enable the watchdog operation or drive WD-EN = 0 to disable the watchdog operation. The WD-EN pin can be toggled any time during the device operation. The diagram shows timing behavior with WD-EN pin control. Watchdog Enable: WD-EN Pin Control Watchdog Enable: WD-EN Pin ControlSET[1:0] = 0b'01 combination can be used to disable watchdog operation with a pinout which offers SET1 and SET0 pins, but does not include WD-EN pin. The SET pin logic states can be changed at any time during watchdog operation. Refer section for additional details regarding SET[1:0] pin behavior. Pinout options A, B offer watchdog timer control using a capacitance connected between CWD and GND pin. A capacitance value higher than recommended or connect to GND leads to watchdog functionality getting disabled. Capacitance based disable operation overrides the other two options mentioned above. Changing capacitance on the fly does not enable or disable watchdog operation. A power supply recycle is needed to detect change in capacitance.Ongoing watchdog frame is terminated when watchdog is disabled. WDO stays deasserted when watchdog operation is disabled. When enabled the device immediately enters tWC frame and start watchdog monitoring operation.tWC WC tSD Watchdog Start Up Delay The TPS3436-Q1 supports watchdog startup delay feature. This feature is activated after power up or after WDO assert event. When tSD frame is active, the device monitors the WDI pin but the WDO output is not asserted. This feature allows time for the host complete boot process before watchdog monitoring can take over. The start up delay helps avoid unexpected WDO assert events during boot. The tSD time is predetermined based on the device part number selected. Refer section for details to map the part number to tSD time. Pinout option A, B are available only in no delay or 10 sec start up delay options. The tSD frame is complete when the time duration selected for tSD is over or host provides a valid transition on the WDI pin. The host must provide a valid transition on the WDI pin during tSD time. The device exits the tSD frame and enters watchdog monitoring phase after valid WDI transition. Failure to provide valid transition on WDI pin triggers the watchdog error by asserting the WDO output pin. The tSD frame is not initiated when the watchdog functionality is enabled using WD-EN pin or SET[1:0] pin combination as described in section. shows the operation for tSD time frame. tSD Frame Behavior tSD Watchdog Start Up DelaySD The TPS3436-Q1 supports watchdog startup delay feature. This feature is activated after power up or after WDO assert event. When tSD frame is active, the device monitors the WDI pin but the WDO output is not asserted. This feature allows time for the host complete boot process before watchdog monitoring can take over. The start up delay helps avoid unexpected WDO assert events during boot. The tSD time is predetermined based on the device part number selected. Refer section for details to map the part number to tSD time. Pinout option A, B are available only in no delay or 10 sec start up delay options. The tSD frame is complete when the time duration selected for tSD is over or host provides a valid transition on the WDI pin. The host must provide a valid transition on the WDI pin during tSD time. The device exits the tSD frame and enters watchdog monitoring phase after valid WDI transition. Failure to provide valid transition on WDI pin triggers the watchdog error by asserting the WDO output pin. The tSD frame is not initiated when the watchdog functionality is enabled using WD-EN pin or SET[1:0] pin combination as described in section. shows the operation for tSD time frame. tSD Frame Behavior The TPS3436-Q1 supports watchdog startup delay feature. This feature is activated after power up or after WDO assert event. When tSD frame is active, the device monitors the WDI pin but the WDO output is not asserted. This feature allows time for the host complete boot process before watchdog monitoring can take over. The start up delay helps avoid unexpected WDO assert events during boot. The tSD time is predetermined based on the device part number selected. Refer section for details to map the part number to tSD time. Pinout option A, B are available only in no delay or 10 sec start up delay options. The tSD frame is complete when the time duration selected for tSD is over or host provides a valid transition on the WDI pin. The host must provide a valid transition on the WDI pin during tSD time. The device exits the tSD frame and enters watchdog monitoring phase after valid WDI transition. Failure to provide valid transition on WDI pin triggers the watchdog error by asserting the WDO output pin. The tSD frame is not initiated when the watchdog functionality is enabled using WD-EN pin or SET[1:0] pin combination as described in section. shows the operation for tSD time frame. tSD Frame Behavior The TPS3436-Q1 supports watchdog startup delay feature. This feature is activated after power up or after WDO assert event. When tSD frame is active, the device monitors the WDI pin but the WDO output is not asserted. This feature allows time for the host complete boot process before watchdog monitoring can take over. The start up delay helps avoid unexpected WDO assert events during boot. The tSD time is predetermined based on the device part number selected. Refer section for details to map the part number to tSD time. Pinout option A, B are available only in no delay or 10 sec start up delay options.TPS3436-Q1SDSD SDThe tSD frame is complete when the time duration selected for tSD is over or host provides a valid transition on the WDI pin. The host must provide a valid transition on the WDI pin during tSD time. The device exits the tSD frame and enters watchdog monitoring phase after valid WDI transition. Failure to provide valid transition on WDI pin triggers the watchdog error by asserting the WDO output pin.SDSDSDSDThe tSD frame is not initiated when the watchdog functionality is enabled using WD-EN pin or SET[1:0] pin combination as described in section.SD shows the operation for tSD time frame.SD tSD Frame Behavior tSD Frame BehaviorSD SET Pin Behavior The TPS3436-Q1 offers one or two SET pins based on the pinout option selected. SET pins offer flexibility to the user to program the tWO timer on the fly to meet various application requirements. Typical use cases where SET pin can be used are Use wide open window timer when host is in sleep mode, change to small timeout operation when host is operational. Watchdog can be used to wake up the host after long duration to perform the application related activities before going back to sleep. Change to wide open window timer when performing system critical tasks to ensure watchdog does not interrupt the critical task. Change timer to application specified interval after the critical task is complete. The tWO timer value for the device is combination of tWC timer selection based on the CWD pin or fixed timer value along with SET pin logic level. The tWC timer value is decided based on the Watchdog Close Time selector in the section. The SET pin logic level is decoded during the device power up. The SET pin value can be changed any time during the operation. SETx pin change which leads to change of watchdog timer value or enable disable state, terminates the ongoing watchdog frame immediately. SETx pins can be updated when WDO output is asserted as well. The updated tWO timer value will be applied after output is deasserted and the tSD timer is over or terminated. For a pinout which offers only SET0 pin to the user, the tWO ratio value is decided based on the Watchdog Open Time Ratio selector field in the orderable part number. Refer for available options. showcases an example of the tWO values for different SET0 logic levels when using Watchdog Close Time setting as option D = 10 msec. tWO Values with SET0 Pin Only (Pin Configuration A) Watchdog Open Time Ratio Selection tWO SET0 = 0 SET0 = 1 A 10 msec 30 msec B 30 msec 70 msec C 70 msec 150 msec D 150 msec 310 msec E 310 msec 630 msec F 630 msec 1270 msec Pinout which offer both SET0 & SET1 pins to the user, the tWO ratio value is decided based on the Watchdog Open Time Ratio selector field in the orderable part number. Refer for available options. Two SETx pins offer 3 different time scaling options. The SET[1:0] = 0b'01 combination disables the watchdog operation. showcases an example of the tWO values for different SET[1:0] logic levels when using Watchdog Close Time setting as option G = 100 msec. The package pin out selected does not offer WD-EN pin. tWO Values with SET0 & SET1 Pins, WD-EN Pin Not Available (Pin Configuration B) Watchdog Open Time Ratio selection tWO SET[1:0] = 0b'00 SET[1:0] = 0b'01 SET[1:0] = 0b'10 SET[1:0] = 0b'11 A 100 msec Watchdog disable 300 msec 1500 msec B 300 msec Watchdog disable 700 msec 3100 msec C 700 msec Watchdog disable 1500 msec 6300 msec D 1500 msec Watchdog disable 3100 msec 12700 msec E 3100 msec Watchdog disable 6300 msec 25500 msec F 6300 msec Watchdog disable 12700 msec 51100 msec Example for Watchdog Close Time setting = 100 msec. Selected pinout option can offer WD-EN pin along with SET[1:0] pins (Pin Configuration C). With this pinout, the WD-EN pin controls watchdog enable and disable operation. The SET[1:0] = 0b'01 combination operates as SET[1:0] = 0b'00. Ensure the tWO value with SETx ratio does not exceed 640 sec. If a selection of close window timer and ratio results in tWO > 640 sec, the timer value will be restricted to 640 sec. to show the timing behavior with respect to SETx status changes. Watchdog Behavior with SETx Pin Status Watchdog Operation with 2 SET Pins Watchdog Operation with 1 SET Pin SET Pin Behavior The TPS3436-Q1 offers one or two SET pins based on the pinout option selected. SET pins offer flexibility to the user to program the tWO timer on the fly to meet various application requirements. Typical use cases where SET pin can be used are Use wide open window timer when host is in sleep mode, change to small timeout operation when host is operational. Watchdog can be used to wake up the host after long duration to perform the application related activities before going back to sleep. Change to wide open window timer when performing system critical tasks to ensure watchdog does not interrupt the critical task. Change timer to application specified interval after the critical task is complete. The tWO timer value for the device is combination of tWC timer selection based on the CWD pin or fixed timer value along with SET pin logic level. The tWC timer value is decided based on the Watchdog Close Time selector in the section. The SET pin logic level is decoded during the device power up. The SET pin value can be changed any time during the operation. SETx pin change which leads to change of watchdog timer value or enable disable state, terminates the ongoing watchdog frame immediately. SETx pins can be updated when WDO output is asserted as well. The updated tWO timer value will be applied after output is deasserted and the tSD timer is over or terminated. For a pinout which offers only SET0 pin to the user, the tWO ratio value is decided based on the Watchdog Open Time Ratio selector field in the orderable part number. Refer for available options. showcases an example of the tWO values for different SET0 logic levels when using Watchdog Close Time setting as option D = 10 msec. tWO Values with SET0 Pin Only (Pin Configuration A) Watchdog Open Time Ratio Selection tWO SET0 = 0 SET0 = 1 A 10 msec 30 msec B 30 msec 70 msec C 70 msec 150 msec D 150 msec 310 msec E 310 msec 630 msec F 630 msec 1270 msec Pinout which offer both SET0 & SET1 pins to the user, the tWO ratio value is decided based on the Watchdog Open Time Ratio selector field in the orderable part number. Refer for available options. Two SETx pins offer 3 different time scaling options. The SET[1:0] = 0b'01 combination disables the watchdog operation. showcases an example of the tWO values for different SET[1:0] logic levels when using Watchdog Close Time setting as option G = 100 msec. The package pin out selected does not offer WD-EN pin. tWO Values with SET0 & SET1 Pins, WD-EN Pin Not Available (Pin Configuration B) Watchdog Open Time Ratio selection tWO SET[1:0] = 0b'00 SET[1:0] = 0b'01 SET[1:0] = 0b'10 SET[1:0] = 0b'11 A 100 msec Watchdog disable 300 msec 1500 msec B 300 msec Watchdog disable 700 msec 3100 msec C 700 msec Watchdog disable 1500 msec 6300 msec D 1500 msec Watchdog disable 3100 msec 12700 msec E 3100 msec Watchdog disable 6300 msec 25500 msec F 6300 msec Watchdog disable 12700 msec 51100 msec Example for Watchdog Close Time setting = 100 msec. Selected pinout option can offer WD-EN pin along with SET[1:0] pins (Pin Configuration C). With this pinout, the WD-EN pin controls watchdog enable and disable operation. The SET[1:0] = 0b'01 combination operates as SET[1:0] = 0b'00. Ensure the tWO value with SETx ratio does not exceed 640 sec. If a selection of close window timer and ratio results in tWO > 640 sec, the timer value will be restricted to 640 sec. to show the timing behavior with respect to SETx status changes. Watchdog Behavior with SETx Pin Status Watchdog Operation with 2 SET Pins Watchdog Operation with 1 SET Pin The TPS3436-Q1 offers one or two SET pins based on the pinout option selected. SET pins offer flexibility to the user to program the tWO timer on the fly to meet various application requirements. Typical use cases where SET pin can be used are Use wide open window timer when host is in sleep mode, change to small timeout operation when host is operational. Watchdog can be used to wake up the host after long duration to perform the application related activities before going back to sleep. Change to wide open window timer when performing system critical tasks to ensure watchdog does not interrupt the critical task. Change timer to application specified interval after the critical task is complete. The tWO timer value for the device is combination of tWC timer selection based on the CWD pin or fixed timer value along with SET pin logic level. The tWC timer value is decided based on the Watchdog Close Time selector in the section. The SET pin logic level is decoded during the device power up. The SET pin value can be changed any time during the operation. SETx pin change which leads to change of watchdog timer value or enable disable state, terminates the ongoing watchdog frame immediately. SETx pins can be updated when WDO output is asserted as well. The updated tWO timer value will be applied after output is deasserted and the tSD timer is over or terminated. For a pinout which offers only SET0 pin to the user, the tWO ratio value is decided based on the Watchdog Open Time Ratio selector field in the orderable part number. Refer for available options. showcases an example of the tWO values for different SET0 logic levels when using Watchdog Close Time setting as option D = 10 msec. tWO Values with SET0 Pin Only (Pin Configuration A) Watchdog Open Time Ratio Selection tWO SET0 = 0 SET0 = 1 A 10 msec 30 msec B 30 msec 70 msec C 70 msec 150 msec D 150 msec 310 msec E 310 msec 630 msec F 630 msec 1270 msec Pinout which offer both SET0 & SET1 pins to the user, the tWO ratio value is decided based on the Watchdog Open Time Ratio selector field in the orderable part number. Refer for available options. Two SETx pins offer 3 different time scaling options. The SET[1:0] = 0b'01 combination disables the watchdog operation. showcases an example of the tWO values for different SET[1:0] logic levels when using Watchdog Close Time setting as option G = 100 msec. The package pin out selected does not offer WD-EN pin. tWO Values with SET0 & SET1 Pins, WD-EN Pin Not Available (Pin Configuration B) Watchdog Open Time Ratio selection tWO SET[1:0] = 0b'00 SET[1:0] = 0b'01 SET[1:0] = 0b'10 SET[1:0] = 0b'11 A 100 msec Watchdog disable 300 msec 1500 msec B 300 msec Watchdog disable 700 msec 3100 msec C 700 msec Watchdog disable 1500 msec 6300 msec D 1500 msec Watchdog disable 3100 msec 12700 msec E 3100 msec Watchdog disable 6300 msec 25500 msec F 6300 msec Watchdog disable 12700 msec 51100 msec Example for Watchdog Close Time setting = 100 msec. Selected pinout option can offer WD-EN pin along with SET[1:0] pins (Pin Configuration C). With this pinout, the WD-EN pin controls watchdog enable and disable operation. The SET[1:0] = 0b'01 combination operates as SET[1:0] = 0b'00. Ensure the tWO value with SETx ratio does not exceed 640 sec. If a selection of close window timer and ratio results in tWO > 640 sec, the timer value will be restricted to 640 sec. to show the timing behavior with respect to SETx status changes. Watchdog Behavior with SETx Pin Status Watchdog Operation with 2 SET Pins Watchdog Operation with 1 SET Pin The TPS3436-Q1 offers one or two SET pins based on the pinout option selected. SET pins offer flexibility to the user to program the tWO timer on the fly to meet various application requirements. Typical use cases where SET pin can be used areTPS3436-Q1WO Use wide open window timer when host is in sleep mode, change to small timeout operation when host is operational. Watchdog can be used to wake up the host after long duration to perform the application related activities before going back to sleep. Change to wide open window timer when performing system critical tasks to ensure watchdog does not interrupt the critical task. Change timer to application specified interval after the critical task is complete. Use wide open window timer when host is in sleep mode, change to small timeout operation when host is operational. Watchdog can be used to wake up the host after long duration to perform the application related activities before going back to sleep.Change to wide open window timer when performing system critical tasks to ensure watchdog does not interrupt the critical task. Change timer to application specified interval after the critical task is complete.The tWO timer value for the device is combination of tWC timer selection based on the CWD pin or fixed timer value along with SET pin logic level. The tWC timer value is decided based on the Watchdog Close Time selector in the section. The SET pin logic level is decoded during the device power up. The SET pin value can be changed any time during the operation. SETx pin change which leads to change of watchdog timer value or enable disable state, terminates the ongoing watchdog frame immediately. SETx pins can be updated when WDO output is asserted as well. The updated tWO timer value will be applied after output is deasserted and the tSD timer is over or terminated.WOWCWC WOSDFor a pinout which offers only SET0 pin to the user, the tWO ratio value is decided based on the Watchdog Open Time Ratio selector field in the orderable part number. Refer for available options. showcases an example of the tWO values for different SET0 logic levels when using Watchdog Close Time setting as option D = 10 msec.WO WO tWO Values with SET0 Pin Only (Pin Configuration A) Watchdog Open Time Ratio Selection tWO SET0 = 0 SET0 = 1 A 10 msec 30 msec B 30 msec 70 msec C 70 msec 150 msec D 150 msec 310 msec E 310 msec 630 msec F 630 msec 1270 msec tWO Values with SET0 Pin Only (Pin Configuration A)WO Watchdog Open Time Ratio Selection tWO SET0 = 0 SET0 = 1 A 10 msec 30 msec B 30 msec 70 msec C 70 msec 150 msec D 150 msec 310 msec E 310 msec 630 msec F 630 msec 1270 msec Watchdog Open Time Ratio Selection tWO SET0 = 0 SET0 = 1 Watchdog Open Time Ratio Selection tWO Watchdog Open Time Ratio Selection Watchdog Open Time Ratio Selection tWO tWO WO SET0 = 0 SET0 = 1 SET0 = 0 SET0 = 0 SET0 = 1 SET0 = 1 A 10 msec 30 msec B 30 msec 70 msec C 70 msec 150 msec D 150 msec 310 msec E 310 msec 630 msec F 630 msec 1270 msec A 10 msec 30 msec A10 msec30 msec B 30 msec 70 msec B30 msec70 msec C 70 msec 150 msec C70 msec150 msec D 150 msec 310 msec D150 msec310 msec E 310 msec 630 msec E310 msec630 msec F 630 msec 1270 msec F630 msec1270 msecPinout which offer both SET0 & SET1 pins to the user, the tWO ratio value is decided based on the Watchdog Open Time Ratio selector field in the orderable part number. Refer for available options. Two SETx pins offer 3 different time scaling options. The SET[1:0] = 0b'01 combination disables the watchdog operation. showcases an example of the tWO values for different SET[1:0] logic levels when using Watchdog Close Time setting as option G = 100 msec. The package pin out selected does not offer WD-EN pin.WO WO tWO Values with SET0 & SET1 Pins, WD-EN Pin Not Available (Pin Configuration B) Watchdog Open Time Ratio selection tWO SET[1:0] = 0b'00 SET[1:0] = 0b'01 SET[1:0] = 0b'10 SET[1:0] = 0b'11 A 100 msec Watchdog disable 300 msec 1500 msec B 300 msec Watchdog disable 700 msec 3100 msec C 700 msec Watchdog disable 1500 msec 6300 msec D 1500 msec Watchdog disable 3100 msec 12700 msec E 3100 msec Watchdog disable 6300 msec 25500 msec F 6300 msec Watchdog disable 12700 msec 51100 msec tWO Values with SET0 & SET1 Pins, WD-EN Pin Not Available (Pin Configuration B)WO Watchdog Open Time Ratio selection tWO SET[1:0] = 0b'00 SET[1:0] = 0b'01 SET[1:0] = 0b'10 SET[1:0] = 0b'11 A 100 msec Watchdog disable 300 msec 1500 msec B 300 msec Watchdog disable 700 msec 3100 msec C 700 msec Watchdog disable 1500 msec 6300 msec D 1500 msec Watchdog disable 3100 msec 12700 msec E 3100 msec Watchdog disable 6300 msec 25500 msec F 6300 msec Watchdog disable 12700 msec 51100 msec Watchdog Open Time Ratio selection tWO SET[1:0] = 0b'00 SET[1:0] = 0b'01 SET[1:0] = 0b'10 SET[1:0] = 0b'11 Watchdog Open Time Ratio selection tWO Watchdog Open Time Ratio selection Watchdog Open Time Ratio selection tWO tWO WO SET[1:0] = 0b'00 SET[1:0] = 0b'01 SET[1:0] = 0b'10 SET[1:0] = 0b'11 SET[1:0] = 0b'00 SET[1:0] = 0b'00 SET[1:0] = 0b'01 SET[1:0] = 0b'01 SET[1:0] = 0b'10 SET[1:0] = 0b'10 SET[1:0] = 0b'11 SET[1:0] = 0b'11 A 100 msec Watchdog disable 300 msec 1500 msec B 300 msec Watchdog disable 700 msec 3100 msec C 700 msec Watchdog disable 1500 msec 6300 msec D 1500 msec Watchdog disable 3100 msec 12700 msec E 3100 msec Watchdog disable 6300 msec 25500 msec F 6300 msec Watchdog disable 12700 msec 51100 msec A 100 msec Watchdog disable 300 msec 1500 msec A100 msecWatchdog disable300 msec1500 msec B 300 msec Watchdog disable 700 msec 3100 msec B300 msecWatchdog disable700 msec3100 msec C 700 msec Watchdog disable 1500 msec 6300 msec C700 msecWatchdog disable1500 msec6300 msec D 1500 msec Watchdog disable 3100 msec 12700 msec D1500 msecWatchdog disable3100 msec12700 msec E 3100 msec Watchdog disable 6300 msec 25500 msec E3100 msecWatchdog disable6300 msec25500 msec F 6300 msec Watchdog disable 12700 msec 51100 msec F6300 msecWatchdog disable12700 msec51100 msec Example for Watchdog Close Time setting = 100 msec. Example for Watchdog Close Time setting = 100 msec.Selected pinout option can offer WD-EN pin along with SET[1:0] pins (Pin Configuration C). With this pinout, the WD-EN pin controls watchdog enable and disable operation. The SET[1:0] = 0b'01 combination operates as SET[1:0] = 0b'00. Ensure the tWO value with SETx ratio does not exceed 640 sec. If a selection of close window timer and ratio results in tWO > 640 sec, the timer value will be restricted to 640 sec.WOWO to show the timing behavior with respect to SETx status changes. Watchdog Behavior with SETx Pin Status Watchdog Behavior with SETx Pin Status Watchdog Operation with 2 SET Pins Watchdog Operation with 2 SET Pins Watchdog Operation with 1 SET Pin Watchdog Operation with 1 SET Pin Manual RESET The TPS3436-Q1 supports manual reset functionality using MR pin. MR pin when driven with voltage lower than 0.3 x VDD, asserts the WDO output. The MR pin has 100 kΩ pull up to VDD. The MR pin can be left floating. The internal pull up makes sure the output is not asserted due to MR pin trigger. The output is deasserted after MR pin voltage rises above 0.7 x VDD voltage. Refer for more details. MR Pin Response Manual RESET The TPS3436-Q1 supports manual reset functionality using MR pin. MR pin when driven with voltage lower than 0.3 x VDD, asserts the WDO output. The MR pin has 100 kΩ pull up to VDD. The MR pin can be left floating. The internal pull up makes sure the output is not asserted due to MR pin trigger. The output is deasserted after MR pin voltage rises above 0.7 x VDD voltage. Refer for more details. MR Pin Response The TPS3436-Q1 supports manual reset functionality using MR pin. MR pin when driven with voltage lower than 0.3 x VDD, asserts the WDO output. The MR pin has 100 kΩ pull up to VDD. The MR pin can be left floating. The internal pull up makes sure the output is not asserted due to MR pin trigger. The output is deasserted after MR pin voltage rises above 0.7 x VDD voltage. Refer for more details. MR Pin Response The TPS3436-Q1 supports manual reset functionality using MR pin. MR pin when driven with voltage lower than 0.3 x VDD, asserts the WDO output. The MR pin has 100 kΩ pull up to VDD. The MR pin can be left floating. The internal pull up makes sure the output is not asserted due to MR pin trigger.TPS3436-Q1MRMRWDOMRMRMRThe output is deasserted after MR pin voltage rises above 0.7 x VDD voltage. Refer for more details.MR MR Pin Response MR Pin ResponseMR WDO Output The TPS3436-Q1 device offers WDO output pin. WDO output is asserted when MR pin voltage is lower than 0.3 X VDD or watchdog timer error is detected. The output will be asserted for tWDO time when any relevant events described above are detected, except for MR event. The time tWDO can be programmed by connecting a capacitor between CRST pin and GND or device will assert tWDO for fixed time duration as selected by orderable part number. Refer section for all available options. describes the relationship between capacitor value and the time tWDO . Ensure the capacitance meets the recommended operating range. Capacitance outside the recommended range can lead to incorrect operation of the device. t WDO (sec) = 4.95 x 106 x CCRST (F) TPS3436-Q1 also offers a unique option of latched output. An orderable with latched output will hold the output in asserted state indefinitely until the device is power cycled or the error condition is addressed. If the output is latched due to MR pin low voltage, the output latch will be released when MR pin voltage rises above 0.7 x VDD level. If the output is latched due to watchdog timer error, the output latch will be released when a WDI negative edge is detected or the device is shutdown and powered up again. shows timing behavior of the device with latched output configuration. Output Latch Timing Behavior WDO Output The TPS3436-Q1 device offers WDO output pin. WDO output is asserted when MR pin voltage is lower than 0.3 X VDD or watchdog timer error is detected. The output will be asserted for tWDO time when any relevant events described above are detected, except for MR event. The time tWDO can be programmed by connecting a capacitor between CRST pin and GND or device will assert tWDO for fixed time duration as selected by orderable part number. Refer section for all available options. describes the relationship between capacitor value and the time tWDO . Ensure the capacitance meets the recommended operating range. Capacitance outside the recommended range can lead to incorrect operation of the device. t WDO (sec) = 4.95 x 106 x CCRST (F) TPS3436-Q1 also offers a unique option of latched output. An orderable with latched output will hold the output in asserted state indefinitely until the device is power cycled or the error condition is addressed. If the output is latched due to MR pin low voltage, the output latch will be released when MR pin voltage rises above 0.7 x VDD level. If the output is latched due to watchdog timer error, the output latch will be released when a WDI negative edge is detected or the device is shutdown and powered up again. shows timing behavior of the device with latched output configuration. Output Latch Timing Behavior The TPS3436-Q1 device offers WDO output pin. WDO output is asserted when MR pin voltage is lower than 0.3 X VDD or watchdog timer error is detected. The output will be asserted for tWDO time when any relevant events described above are detected, except for MR event. The time tWDO can be programmed by connecting a capacitor between CRST pin and GND or device will assert tWDO for fixed time duration as selected by orderable part number. Refer section for all available options. describes the relationship between capacitor value and the time tWDO . Ensure the capacitance meets the recommended operating range. Capacitance outside the recommended range can lead to incorrect operation of the device. t WDO (sec) = 4.95 x 106 x CCRST (F) TPS3436-Q1 also offers a unique option of latched output. An orderable with latched output will hold the output in asserted state indefinitely until the device is power cycled or the error condition is addressed. If the output is latched due to MR pin low voltage, the output latch will be released when MR pin voltage rises above 0.7 x VDD level. If the output is latched due to watchdog timer error, the output latch will be released when a WDI negative edge is detected or the device is shutdown and powered up again. shows timing behavior of the device with latched output configuration. Output Latch Timing Behavior The TPS3436-Q1 device offers WDO output pin. WDO output is asserted when MR pin voltage is lower than 0.3 X VDD or watchdog timer error is detected.TPS3436-Q1MRThe output will be asserted for tWDO time when any relevant events described above are detected, except for MR event. The time tWDO can be programmed by connecting a capacitor between CRST pin and GND or device will assert tWDO for fixed time duration as selected by orderable part number. Refer section for all available options.tWDO WDO, except for MR eventMRtWDO WDOtWDO WDO describes the relationship between capacitor value and the time tWDO . Ensure the capacitance meets the recommended operating range. Capacitance outside the recommended range can lead to incorrect operation of the device.tWDO WDO t WDO (sec) = 4.95 x 106 x CCRST (F) t WDO (sec) = 4.95 x 106 x CCRST (F) WDO WDO6CRST TPS3436-Q1 also offers a unique option of latched output. An orderable with latched output will hold the output in asserted state indefinitely until the device is power cycled or the error condition is addressed. If the output is latched due to MR pin low voltage, the output latch will be released when MR pin voltage rises above 0.7 x VDD level. If the output is latched due to watchdog timer error, the output latch will be released when a WDI negative edge is detected or the device is shutdown and powered up again. shows timing behavior of the device with latched output configuration.TPS3436-Q1MRMRDD Output Latch Timing Behavior Output Latch Timing Behavior Device Functional Modes #GUID-B008A25A-278A-4B38-AFBB-A738DE66DE26/TABLE_UZD_NXV_HVB summarizes the functional modes of the TPS3436-Q1. Device Functional Modes VDD WATCHDOG STATUS WDI WDO VDD < VPOR Not Applicable — Undefined VPOR ≤ VDD < VDDmin Not Applicable Ignored High VDD ≥ VDDmin Disabled Ignored High Enabled tWC(max) ≤ tpulse 1 ≤ tWC(max) + tWO(min) High Enabled tWC(max) > tpulse 1 Low Enabled tWC(max) + tWO(max) < tpulse 1 Low Where tpulse is the time between falling edges on WDI. Device Functional Modes #GUID-B008A25A-278A-4B38-AFBB-A738DE66DE26/TABLE_UZD_NXV_HVB summarizes the functional modes of the TPS3436-Q1. Device Functional Modes VDD WATCHDOG STATUS WDI WDO VDD < VPOR Not Applicable — Undefined VPOR ≤ VDD < VDDmin Not Applicable Ignored High VDD ≥ VDDmin Disabled Ignored High Enabled tWC(max) ≤ tpulse 1 ≤ tWC(max) + tWO(min) High Enabled tWC(max) > tpulse 1 Low Enabled tWC(max) + tWO(max) < tpulse 1 Low Where tpulse is the time between falling edges on WDI. #GUID-B008A25A-278A-4B38-AFBB-A738DE66DE26/TABLE_UZD_NXV_HVB summarizes the functional modes of the TPS3436-Q1. Device Functional Modes VDD WATCHDOG STATUS WDI WDO VDD < VPOR Not Applicable — Undefined VPOR ≤ VDD < VDDmin Not Applicable Ignored High VDD ≥ VDDmin Disabled Ignored High Enabled tWC(max) ≤ tpulse 1 ≤ tWC(max) + tWO(min) High Enabled tWC(max) > tpulse 1 Low Enabled tWC(max) + tWO(max) < tpulse 1 Low Where tpulse is the time between falling edges on WDI. #GUID-B008A25A-278A-4B38-AFBB-A738DE66DE26/TABLE_UZD_NXV_HVB summarizes the functional modes of the TPS3436-Q1. #GUID-B008A25A-278A-4B38-AFBB-A738DE66DE26/TABLE_UZD_NXV_HVB #GUID-B008A25A-278A-4B38-AFBB-A738DE66DE26/TABLE_UZD_NXV_HVBTPS3436-Q1 Device Functional Modes VDD WATCHDOG STATUS WDI WDO VDD < VPOR Not Applicable — Undefined VPOR ≤ VDD < VDDmin Not Applicable Ignored High VDD ≥ VDDmin Disabled Ignored High Enabled tWC(max) ≤ tpulse 1 ≤ tWC(max) + tWO(min) High Enabled tWC(max) > tpulse 1 Low Enabled tWC(max) + tWO(max) < tpulse 1 Low Device Functional Modes VDD WATCHDOG STATUS WDI WDO VDD < VPOR Not Applicable — Undefined VPOR ≤ VDD < VDDmin Not Applicable Ignored High VDD ≥ VDDmin Disabled Ignored High Enabled tWC(max) ≤ tpulse 1 ≤ tWC(max) + tWO(min) High Enabled tWC(max) > tpulse 1 Low Enabled tWC(max) + tWO(max) < tpulse 1 Low VDD WATCHDOG STATUS WDI WDO VDD WATCHDOG STATUS WDI WDO VDDWATCHDOG STATUSWDI WDO WDO VDD < VPOR Not Applicable — Undefined VPOR ≤ VDD < VDDmin Not Applicable Ignored High VDD ≥ VDDmin Disabled Ignored High Enabled tWC(max) ≤ tpulse 1 ≤ tWC(max) + tWO(min) High Enabled tWC(max) > tpulse 1 Low Enabled tWC(max) + tWO(max) < tpulse 1 Low VDD < VPOR Not Applicable — Undefined VDD < VPOR DDPORNot Applicable—Undefined VPOR ≤ VDD < VDDmin Not Applicable Ignored High VPOR ≤ VDD < VDDmin PORDDDDminNot ApplicableIgnoredHigh VDD ≥ VDDmin Disabled Ignored High VDD ≥ VDDmin DDDDminDisabledIgnoredHigh Enabled tWC(max) ≤ tpulse 1 ≤ tWC(max) + tWO(min) High EnabledtWC(max) ≤ tpulse 1 ≤ tWC(max) + tWO(min) WC(max)pulse1WC(max)WO(min)High Enabled tWC(max) > tpulse 1 Low EnabledtWC(max) > tpulse 1 WC(max)pulse1Low Enabled tWC(max) + tWO(max) < tpulse 1 Low EnabledtWC(max) + tWO(max) < tpulse 1 WC(max)WO(max)pulse1Low Where tpulse is the time between falling edges on WDI. Where tpulse is the time between falling edges on WDI.pulse Application and Implementation Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. Application Information The following sections describe in detail proper device implementation, depending on the final application requirements. Output Assert Delay The TPS3436-Q1 features two options for setting the output assert delay (tWDO ): using a fixed timing and programming the timing through an external capacitor. Factory-Programmed Output Assert Delay Timing Fixed output assert delay timings are available using pinout C . Using these timings enables a high-precision, 10% accurate output assert delay timing. Adjustable Capacitor Timing The TPS3436-Q1 also utilizes a programmable output assert delay, using a precision current source to charge an external capacitor upon device startup. The typical delay time resulting from a given external capacitance on the CRST pin can be calculated by #GUID-D1D35606-1121-467A-A793-EC910F60F861/T4523365-12, where tWDO is the output assert delay time in seconds and CCRST is the capacitance in microfarads. tWDO (sec) = 4.95 × 106 × CCRST (F) Note that in order to minimize the difference between the calculated output assert delay time and the actual output assert delay time, use a high-quality ceramic dielectric COG, X5R, or X7R capacitor and minimize parasitic board capacitance around this pin. #GUID-D1D35606-1121-467A-A793-EC910F60F861/SBVS3011026 lists the output assert delay time for ideal capacitor values. Output Assert Delay Time for Common Ideal Capacitor Values CCRST OUTPUT ASSERTDELAY TIME ( tWDO ) UNIT MIN#GUID-D1D35606-1121-467A-A793-EC910F60F861/T4523365-39 TYP MAX#GUID-D1D35606-1121-467A-A793-EC910F60F861/T4523365-39 10 nF 39.6 49.5 59.4 ms 100 nF 396 495 594 ms 1 μF 3960 4950 5940 ms Minimum and maximum values are calculated using ideal capacitors. Watchdog Window Functionality The TPS3436-Q1 features two options for setting the close window watchdog timer (tWC ): using a fixed timing and programming the timing through an external capacitor. Factory-Programmed Timing Options Fixed watchdog timeout options are available using pinout C. Using these timings enables a high-precision, 10% accurate watchdog timer tWC . Adjustable Capacitor Timing Adjustable tWC timing is achievable by connecting a capacitor to the CWD pin. If this method is used, please consult to for equations to calculate typical tWC values using ideal capacitors as the effect of CCWD depends on the SETx pin values. Capacitor tolerances cause the actual device timing to vary such that the minimum of tWC can decrease and the maximum of tWC can increase by the capacitor tolerance. For the most accurate timing, use ceramic capacitors with COG dielectric material. Typical Applications Design 1: Monitoring a Microcontroller Watchdog During Operational and Sleep Modes The TPS3436-Q1 can utilize high-accuracy voltage monitoring and on-the-fly SETx assigning to monitor a microcontroller that has both an operational and sleep mode. Microcontroller Window Watchdog Monitoring with Sleep Watchdog Mode Design Requirements PARAMETER DESIGN REQUIREMENT DESIGN RESULT Window Close Time During Operation Typical tWC of 50 ms during operation Typical tWC of 50ms Window Open Time During Operation Typical tWO of 1.4 s during operation Typical tWO of 1.55 s Window Close Time During Sleep Typical tWC of 50 ms during sleep Typical tWC of 50ms Window Open Time During Sleep Typical tWO of 12 s during sleep Typical tWO of 12.75 s Output Assert Delay Typical tWDO of 200 ms Typical tWDO of 200 ms Output logic voltage Open-drain Open-drain Maximum device current consumption 20 µA 250 nA typical current consumption Detailed Design Procedure Determining Window Timings During Operation and Sleep Modes The TPS3436-Q1 allows for precise 10% accurate watchdog timings. This application requires two different window timings in order to maximize power efficiency: one for the microcontroller's operational state and one for its sleep state. To achieve this, the host can reassign the SETx pins when it transitions between states. A window close time, tWC, of 50 ms typical is chosen because of the application's 50 ms typical tWC requirement. The application requires a typical watchdog open time, tWO, of 1.4 s during operation and a tWO of 12 s during sleep. Thus, the possible variant options are narrowed to TPS3436xxFExDDFRQ1. Meeting the Output Assert Delay The TPS3436-Q1 features two options for selecting reset delays: fixed delays and capacitor-programmable delays. The TPS3436-Q1 supports only fixed watchdog timings and fixed output assert delays or programmable watchdog timings and programmable output assert delays. The application requires a 200 ms minimum output assert delay, thus output assert delay option G is used. Because of these requirements and no need for a startup delay, the TPS3436CAFEGDDFRQ1 is used. Calculating the WDO Pullup Resistor The TPS3436-Q1 uses an open-drain configuration for the WDO circuit, as shown in . When the FET is off, the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET attempts to pull the drain to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to ensure that VOL is below its maximum value. To choose the proper pullup resistor, there are three key specifications to keep in mind: the pullup voltage (VPU), the recommended maximum WDO pin current (IRST), and VOL. The maximum VOL is 0.3 V, meaning that the effective resistor divider created must be able to bring the voltage on the reset pin below 0.3 V with IRST kept below 2 mA for VDD ≥ 3 V and 500 μA for VDD = 1.5 V. For this example, with a VPU =VDD = 1.5 V, a resistor must be chosen to keep IRST below 500 μA because this value is the maximum consumption current allowed. To ensure this specification is met, a pullup resistor value of 10 kΩ was selected, which sinks a maximum of 180 μA when WDO is asserted. Open-Drain RESET Configuration Power Supply Recommendations This device is designed to operate from an input supply with a voltage range between 1.04 V and 6 V. An input supply capacitor is not required for this device; however, if the input supply is noisy, then good analog practice is to place a 0.1-µF capacitor between the VDD pin and the GND pin. Layout Layout Guidelines Make sure that the connection to the VDD pin is low impedance. Good analog design practice recommends placing a 0.1-µF ceramic capacitor as near as possible to the VDD pin. If a capacitor is not connected to the CRST pin, then minimize parasitic capacitance on this pin so the WDO delay time is not adversely affected. Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a 0.1-µF ceramic capacitor as near as possible to the VDD pin. Place CCRST capacitor as close as possible to the CRST pin. Place CCWD capacitor as close as possible to the CWD pin. Place the pullup resistor on the WDO pin as close to the pin as possible. Layout Example Typical Layout for the Pinout C of TPS3436-Q1 Application and Implementation Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. Application Information The following sections describe in detail proper device implementation, depending on the final application requirements. Output Assert Delay The TPS3436-Q1 features two options for setting the output assert delay (tWDO ): using a fixed timing and programming the timing through an external capacitor. Factory-Programmed Output Assert Delay Timing Fixed output assert delay timings are available using pinout C . Using these timings enables a high-precision, 10% accurate output assert delay timing. Adjustable Capacitor Timing The TPS3436-Q1 also utilizes a programmable output assert delay, using a precision current source to charge an external capacitor upon device startup. The typical delay time resulting from a given external capacitance on the CRST pin can be calculated by #GUID-D1D35606-1121-467A-A793-EC910F60F861/T4523365-12, where tWDO is the output assert delay time in seconds and CCRST is the capacitance in microfarads. tWDO (sec) = 4.95 × 106 × CCRST (F) Note that in order to minimize the difference between the calculated output assert delay time and the actual output assert delay time, use a high-quality ceramic dielectric COG, X5R, or X7R capacitor and minimize parasitic board capacitance around this pin. #GUID-D1D35606-1121-467A-A793-EC910F60F861/SBVS3011026 lists the output assert delay time for ideal capacitor values. Output Assert Delay Time for Common Ideal Capacitor Values CCRST OUTPUT ASSERTDELAY TIME ( tWDO ) UNIT MIN#GUID-D1D35606-1121-467A-A793-EC910F60F861/T4523365-39 TYP MAX#GUID-D1D35606-1121-467A-A793-EC910F60F861/T4523365-39 10 nF 39.6 49.5 59.4 ms 100 nF 396 495 594 ms 1 μF 3960 4950 5940 ms Minimum and maximum values are calculated using ideal capacitors. Watchdog Window Functionality The TPS3436-Q1 features two options for setting the close window watchdog timer (tWC ): using a fixed timing and programming the timing through an external capacitor. Factory-Programmed Timing Options Fixed watchdog timeout options are available using pinout C. Using these timings enables a high-precision, 10% accurate watchdog timer tWC . Adjustable Capacitor Timing Adjustable tWC timing is achievable by connecting a capacitor to the CWD pin. If this method is used, please consult to for equations to calculate typical tWC values using ideal capacitors as the effect of CCWD depends on the SETx pin values. Capacitor tolerances cause the actual device timing to vary such that the minimum of tWC can decrease and the maximum of tWC can increase by the capacitor tolerance. For the most accurate timing, use ceramic capacitors with COG dielectric material. Application Information The following sections describe in detail proper device implementation, depending on the final application requirements. The following sections describe in detail proper device implementation, depending on the final application requirements. The following sections describe in detail proper device implementation, depending on the final application requirements. Output Assert Delay The TPS3436-Q1 features two options for setting the output assert delay (tWDO ): using a fixed timing and programming the timing through an external capacitor. Factory-Programmed Output Assert Delay Timing Fixed output assert delay timings are available using pinout C . Using these timings enables a high-precision, 10% accurate output assert delay timing. Adjustable Capacitor Timing The TPS3436-Q1 also utilizes a programmable output assert delay, using a precision current source to charge an external capacitor upon device startup. The typical delay time resulting from a given external capacitance on the CRST pin can be calculated by #GUID-D1D35606-1121-467A-A793-EC910F60F861/T4523365-12, where tWDO is the output assert delay time in seconds and CCRST is the capacitance in microfarads. tWDO (sec) = 4.95 × 106 × CCRST (F) Note that in order to minimize the difference between the calculated output assert delay time and the actual output assert delay time, use a high-quality ceramic dielectric COG, X5R, or X7R capacitor and minimize parasitic board capacitance around this pin. #GUID-D1D35606-1121-467A-A793-EC910F60F861/SBVS3011026 lists the output assert delay time for ideal capacitor values. Output Assert Delay Time for Common Ideal Capacitor Values CCRST OUTPUT ASSERTDELAY TIME ( tWDO ) UNIT MIN#GUID-D1D35606-1121-467A-A793-EC910F60F861/T4523365-39 TYP MAX#GUID-D1D35606-1121-467A-A793-EC910F60F861/T4523365-39 10 nF 39.6 49.5 59.4 ms 100 nF 396 495 594 ms 1 μF 3960 4950 5940 ms Minimum and maximum values are calculated using ideal capacitors. Output Assert Delay The TPS3436-Q1 features two options for setting the output assert delay (tWDO ): using a fixed timing and programming the timing through an external capacitor. The TPS3436-Q1 features two options for setting the output assert delay (tWDO ): using a fixed timing and programming the timing through an external capacitor. The TPS3436-Q1 features two options for setting the output assert delay (tWDO ): using a fixed timing and programming the timing through an external capacitor.TPS3436-Q1tWDO WDO Factory-Programmed Output Assert Delay Timing Fixed output assert delay timings are available using pinout C . Using these timings enables a high-precision, 10% accurate output assert delay timing. Factory-Programmed Output Assert Delay Timing Fixed output assert delay timings are available using pinout C . Using these timings enables a high-precision, 10% accurate output assert delay timing. Fixed output assert delay timings are available using pinout C . Using these timings enables a high-precision, 10% accurate output assert delay timing. Fixed output assert delay timings are available using pinout C . Using these timings enables a high-precision, 10% accurate output assert delay timing. Adjustable Capacitor Timing The TPS3436-Q1 also utilizes a programmable output assert delay, using a precision current source to charge an external capacitor upon device startup. The typical delay time resulting from a given external capacitance on the CRST pin can be calculated by #GUID-D1D35606-1121-467A-A793-EC910F60F861/T4523365-12, where tWDO is the output assert delay time in seconds and CCRST is the capacitance in microfarads. tWDO (sec) = 4.95 × 106 × CCRST (F) Note that in order to minimize the difference between the calculated output assert delay time and the actual output assert delay time, use a high-quality ceramic dielectric COG, X5R, or X7R capacitor and minimize parasitic board capacitance around this pin. #GUID-D1D35606-1121-467A-A793-EC910F60F861/SBVS3011026 lists the output assert delay time for ideal capacitor values. Output Assert Delay Time for Common Ideal Capacitor Values CCRST OUTPUT ASSERTDELAY TIME ( tWDO ) UNIT MIN#GUID-D1D35606-1121-467A-A793-EC910F60F861/T4523365-39 TYP MAX#GUID-D1D35606-1121-467A-A793-EC910F60F861/T4523365-39 10 nF 39.6 49.5 59.4 ms 100 nF 396 495 594 ms 1 μF 3960 4950 5940 ms Minimum and maximum values are calculated using ideal capacitors. Adjustable Capacitor Timing The TPS3436-Q1 also utilizes a programmable output assert delay, using a precision current source to charge an external capacitor upon device startup. The typical delay time resulting from a given external capacitance on the CRST pin can be calculated by #GUID-D1D35606-1121-467A-A793-EC910F60F861/T4523365-12, where tWDO is the output assert delay time in seconds and CCRST is the capacitance in microfarads. tWDO (sec) = 4.95 × 106 × CCRST (F) Note that in order to minimize the difference between the calculated output assert delay time and the actual output assert delay time, use a high-quality ceramic dielectric COG, X5R, or X7R capacitor and minimize parasitic board capacitance around this pin. #GUID-D1D35606-1121-467A-A793-EC910F60F861/SBVS3011026 lists the output assert delay time for ideal capacitor values. Output Assert Delay Time for Common Ideal Capacitor Values CCRST OUTPUT ASSERTDELAY TIME ( tWDO ) UNIT MIN#GUID-D1D35606-1121-467A-A793-EC910F60F861/T4523365-39 TYP MAX#GUID-D1D35606-1121-467A-A793-EC910F60F861/T4523365-39 10 nF 39.6 49.5 59.4 ms 100 nF 396 495 594 ms 1 μF 3960 4950 5940 ms Minimum and maximum values are calculated using ideal capacitors. The TPS3436-Q1 also utilizes a programmable output assert delay, using a precision current source to charge an external capacitor upon device startup. The typical delay time resulting from a given external capacitance on the CRST pin can be calculated by #GUID-D1D35606-1121-467A-A793-EC910F60F861/T4523365-12, where tWDO is the output assert delay time in seconds and CCRST is the capacitance in microfarads. tWDO (sec) = 4.95 × 106 × CCRST (F) Note that in order to minimize the difference between the calculated output assert delay time and the actual output assert delay time, use a high-quality ceramic dielectric COG, X5R, or X7R capacitor and minimize parasitic board capacitance around this pin. #GUID-D1D35606-1121-467A-A793-EC910F60F861/SBVS3011026 lists the output assert delay time for ideal capacitor values. Output Assert Delay Time for Common Ideal Capacitor Values CCRST OUTPUT ASSERTDELAY TIME ( tWDO ) UNIT MIN#GUID-D1D35606-1121-467A-A793-EC910F60F861/T4523365-39 TYP MAX#GUID-D1D35606-1121-467A-A793-EC910F60F861/T4523365-39 10 nF 39.6 49.5 59.4 ms 100 nF 396 495 594 ms 1 μF 3960 4950 5940 ms Minimum and maximum values are calculated using ideal capacitors. The TPS3436-Q1 also utilizes a programmable output assert delay, using a precision current source to charge an external capacitor upon device startup. The typical delay time resulting from a given external capacitance on the CRST pin can be calculated by #GUID-D1D35606-1121-467A-A793-EC910F60F861/T4523365-12, where tWDO is the output assert delay time in seconds and CCRST is the capacitance in microfarads.TPS3436-Q1#GUID-D1D35606-1121-467A-A793-EC910F60F861/T4523365-12 tWDO WDOCRST tWDO (sec) = 4.95 × 106 × CCRST (F) tWDO WDO6CRSTNote that in order to minimize the difference between the calculated output assert delay time and the actual output assert delay time, use a high-quality ceramic dielectric COG, X5R, or X7R capacitor and minimize parasitic board capacitance around this pin. #GUID-D1D35606-1121-467A-A793-EC910F60F861/SBVS3011026 lists the output assert delay time for ideal capacitor values.#GUID-D1D35606-1121-467A-A793-EC910F60F861/SBVS3011026 Output Assert Delay Time for Common Ideal Capacitor Values CCRST OUTPUT ASSERTDELAY TIME ( tWDO ) UNIT MIN#GUID-D1D35606-1121-467A-A793-EC910F60F861/T4523365-39 TYP MAX#GUID-D1D35606-1121-467A-A793-EC910F60F861/T4523365-39 10 nF 39.6 49.5 59.4 ms 100 nF 396 495 594 ms 1 μF 3960 4950 5940 ms Output Assert Delay Time for Common Ideal Capacitor Values CCRST OUTPUT ASSERTDELAY TIME ( tWDO ) UNIT MIN#GUID-D1D35606-1121-467A-A793-EC910F60F861/T4523365-39 TYP MAX#GUID-D1D35606-1121-467A-A793-EC910F60F861/T4523365-39 10 nF 39.6 49.5 59.4 ms 100 nF 396 495 594 ms 1 μF 3960 4950 5940 ms CCRST OUTPUT ASSERTDELAY TIME ( tWDO ) UNIT MIN#GUID-D1D35606-1121-467A-A793-EC910F60F861/T4523365-39 TYP MAX#GUID-D1D35606-1121-467A-A793-EC910F60F861/T4523365-39 CCRST OUTPUT ASSERTDELAY TIME ( tWDO ) UNIT CCRST CRST OUTPUT ASSERTDELAY TIME ( tWDO )OUTPUT ASSERT tWDO WDOUNIT MIN#GUID-D1D35606-1121-467A-A793-EC910F60F861/T4523365-39 TYP MAX#GUID-D1D35606-1121-467A-A793-EC910F60F861/T4523365-39 MIN#GUID-D1D35606-1121-467A-A793-EC910F60F861/T4523365-39 #GUID-D1D35606-1121-467A-A793-EC910F60F861/T4523365-39TYPMAX#GUID-D1D35606-1121-467A-A793-EC910F60F861/T4523365-39 #GUID-D1D35606-1121-467A-A793-EC910F60F861/T4523365-39 10 nF 39.6 49.5 59.4 ms 100 nF 396 495 594 ms 1 μF 3960 4950 5940 ms 10 nF 39.6 49.5 59.4 ms 10 nF 39.6 39.649.5 59.4 59.4ms 100 nF 396 495 594 ms 100 nF 396 396 495 495 594 594ms 1 μF 3960 4950 5940 ms 1 μF 3960 3960 4950 4950 5940 5940ms Minimum and maximum values are calculated using ideal capacitors. Minimum and maximum values are calculated using ideal capacitors. Watchdog Window Functionality The TPS3436-Q1 features two options for setting the close window watchdog timer (tWC ): using a fixed timing and programming the timing through an external capacitor. Factory-Programmed Timing Options Fixed watchdog timeout options are available using pinout C. Using these timings enables a high-precision, 10% accurate watchdog timer tWC . Adjustable Capacitor Timing Adjustable tWC timing is achievable by connecting a capacitor to the CWD pin. If this method is used, please consult to for equations to calculate typical tWC values using ideal capacitors as the effect of CCWD depends on the SETx pin values. Capacitor tolerances cause the actual device timing to vary such that the minimum of tWC can decrease and the maximum of tWC can increase by the capacitor tolerance. For the most accurate timing, use ceramic capacitors with COG dielectric material. Watchdog Window FunctionalityWindow The TPS3436-Q1 features two options for setting the close window watchdog timer (tWC ): using a fixed timing and programming the timing through an external capacitor. The TPS3436-Q1 features two options for setting the close window watchdog timer (tWC ): using a fixed timing and programming the timing through an external capacitor. The TPS3436-Q1 features two options for setting the close window watchdog timer (tWC ): using a fixed timing and programming the timing through an external capacitor.TPS3436-Q1close window tWC WC Factory-Programmed Timing Options Fixed watchdog timeout options are available using pinout C. Using these timings enables a high-precision, 10% accurate watchdog timer tWC . Factory-Programmed Timing Options Fixed watchdog timeout options are available using pinout C. Using these timings enables a high-precision, 10% accurate watchdog timer tWC . Fixed watchdog timeout options are available using pinout C. Using these timings enables a high-precision, 10% accurate watchdog timer tWC . Fixed watchdog timeout options are available using pinout C. Using these timings enables a high-precision, 10% accurate watchdog timer tWC .tWC WC Adjustable Capacitor Timing Adjustable tWC timing is achievable by connecting a capacitor to the CWD pin. If this method is used, please consult to for equations to calculate typical tWC values using ideal capacitors as the effect of CCWD depends on the SETx pin values. Capacitor tolerances cause the actual device timing to vary such that the minimum of tWC can decrease and the maximum of tWC can increase by the capacitor tolerance. For the most accurate timing, use ceramic capacitors with COG dielectric material. Adjustable Capacitor Timing Adjustable tWC timing is achievable by connecting a capacitor to the CWD pin. If this method is used, please consult to for equations to calculate typical tWC values using ideal capacitors as the effect of CCWD depends on the SETx pin values. Capacitor tolerances cause the actual device timing to vary such that the minimum of tWC can decrease and the maximum of tWC can increase by the capacitor tolerance. For the most accurate timing, use ceramic capacitors with COG dielectric material. Adjustable tWC timing is achievable by connecting a capacitor to the CWD pin. If this method is used, please consult to for equations to calculate typical tWC values using ideal capacitors as the effect of CCWD depends on the SETx pin values. Capacitor tolerances cause the actual device timing to vary such that the minimum of tWC can decrease and the maximum of tWC can increase by the capacitor tolerance. For the most accurate timing, use ceramic capacitors with COG dielectric material. Adjustable tWC timing is achievable by connecting a capacitor to the CWD pin. If this method is used, please consult to for equations to calculate typical tWC values using ideal capacitors as the effect of CCWD depends on the SETx pin values. Capacitor tolerances cause the actual device timing to vary such that the minimum of tWC can decrease and the maximum of tWC can increase by the capacitor tolerance. For the most accurate timing, use ceramic capacitors with COG dielectric material.tWC WC to for equations to calculate typical tWC values using ideal capacitors as the effect of CCWD depends on the SETx pin values.WCCWDtWC WCtWC WC Typical Applications Design 1: Monitoring a Microcontroller Watchdog During Operational and Sleep Modes The TPS3436-Q1 can utilize high-accuracy voltage monitoring and on-the-fly SETx assigning to monitor a microcontroller that has both an operational and sleep mode. Microcontroller Window Watchdog Monitoring with Sleep Watchdog Mode Design Requirements PARAMETER DESIGN REQUIREMENT DESIGN RESULT Window Close Time During Operation Typical tWC of 50 ms during operation Typical tWC of 50ms Window Open Time During Operation Typical tWO of 1.4 s during operation Typical tWO of 1.55 s Window Close Time During Sleep Typical tWC of 50 ms during sleep Typical tWC of 50ms Window Open Time During Sleep Typical tWO of 12 s during sleep Typical tWO of 12.75 s Output Assert Delay Typical tWDO of 200 ms Typical tWDO of 200 ms Output logic voltage Open-drain Open-drain Maximum device current consumption 20 µA 250 nA typical current consumption Detailed Design Procedure Determining Window Timings During Operation and Sleep Modes The TPS3436-Q1 allows for precise 10% accurate watchdog timings. This application requires two different window timings in order to maximize power efficiency: one for the microcontroller's operational state and one for its sleep state. To achieve this, the host can reassign the SETx pins when it transitions between states. A window close time, tWC, of 50 ms typical is chosen because of the application's 50 ms typical tWC requirement. The application requires a typical watchdog open time, tWO, of 1.4 s during operation and a tWO of 12 s during sleep. Thus, the possible variant options are narrowed to TPS3436xxFExDDFRQ1. Meeting the Output Assert Delay The TPS3436-Q1 features two options for selecting reset delays: fixed delays and capacitor-programmable delays. The TPS3436-Q1 supports only fixed watchdog timings and fixed output assert delays or programmable watchdog timings and programmable output assert delays. The application requires a 200 ms minimum output assert delay, thus output assert delay option G is used. Because of these requirements and no need for a startup delay, the TPS3436CAFEGDDFRQ1 is used. Calculating the WDO Pullup Resistor The TPS3436-Q1 uses an open-drain configuration for the WDO circuit, as shown in . When the FET is off, the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET attempts to pull the drain to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to ensure that VOL is below its maximum value. To choose the proper pullup resistor, there are three key specifications to keep in mind: the pullup voltage (VPU), the recommended maximum WDO pin current (IRST), and VOL. The maximum VOL is 0.3 V, meaning that the effective resistor divider created must be able to bring the voltage on the reset pin below 0.3 V with IRST kept below 2 mA for VDD ≥ 3 V and 500 μA for VDD = 1.5 V. For this example, with a VPU =VDD = 1.5 V, a resistor must be chosen to keep IRST below 500 μA because this value is the maximum consumption current allowed. To ensure this specification is met, a pullup resistor value of 10 kΩ was selected, which sinks a maximum of 180 μA when WDO is asserted. Open-Drain RESET Configuration Typical Applications Design 1: Monitoring a Microcontroller Watchdog During Operational and Sleep Modes The TPS3436-Q1 can utilize high-accuracy voltage monitoring and on-the-fly SETx assigning to monitor a microcontroller that has both an operational and sleep mode. Microcontroller Window Watchdog Monitoring with Sleep Watchdog Mode Design Requirements PARAMETER DESIGN REQUIREMENT DESIGN RESULT Window Close Time During Operation Typical tWC of 50 ms during operation Typical tWC of 50ms Window Open Time During Operation Typical tWO of 1.4 s during operation Typical tWO of 1.55 s Window Close Time During Sleep Typical tWC of 50 ms during sleep Typical tWC of 50ms Window Open Time During Sleep Typical tWO of 12 s during sleep Typical tWO of 12.75 s Output Assert Delay Typical tWDO of 200 ms Typical tWDO of 200 ms Output logic voltage Open-drain Open-drain Maximum device current consumption 20 µA 250 nA typical current consumption Detailed Design Procedure Determining Window Timings During Operation and Sleep Modes The TPS3436-Q1 allows for precise 10% accurate watchdog timings. This application requires two different window timings in order to maximize power efficiency: one for the microcontroller's operational state and one for its sleep state. To achieve this, the host can reassign the SETx pins when it transitions between states. A window close time, tWC, of 50 ms typical is chosen because of the application's 50 ms typical tWC requirement. The application requires a typical watchdog open time, tWO, of 1.4 s during operation and a tWO of 12 s during sleep. Thus, the possible variant options are narrowed to TPS3436xxFExDDFRQ1. Meeting the Output Assert Delay The TPS3436-Q1 features two options for selecting reset delays: fixed delays and capacitor-programmable delays. The TPS3436-Q1 supports only fixed watchdog timings and fixed output assert delays or programmable watchdog timings and programmable output assert delays. The application requires a 200 ms minimum output assert delay, thus output assert delay option G is used. Because of these requirements and no need for a startup delay, the TPS3436CAFEGDDFRQ1 is used. Calculating the WDO Pullup Resistor The TPS3436-Q1 uses an open-drain configuration for the WDO circuit, as shown in . When the FET is off, the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET attempts to pull the drain to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to ensure that VOL is below its maximum value. To choose the proper pullup resistor, there are three key specifications to keep in mind: the pullup voltage (VPU), the recommended maximum WDO pin current (IRST), and VOL. The maximum VOL is 0.3 V, meaning that the effective resistor divider created must be able to bring the voltage on the reset pin below 0.3 V with IRST kept below 2 mA for VDD ≥ 3 V and 500 μA for VDD = 1.5 V. For this example, with a VPU =VDD = 1.5 V, a resistor must be chosen to keep IRST below 500 μA because this value is the maximum consumption current allowed. To ensure this specification is met, a pullup resistor value of 10 kΩ was selected, which sinks a maximum of 180 μA when WDO is asserted. Open-Drain RESET Configuration Design 1: Monitoring a Microcontroller Watchdog During Operational and Sleep Modes The TPS3436-Q1 can utilize high-accuracy voltage monitoring and on-the-fly SETx assigning to monitor a microcontroller that has both an operational and sleep mode. Microcontroller Window Watchdog Monitoring with Sleep Watchdog Mode The TPS3436-Q1 can utilize high-accuracy voltage monitoring and on-the-fly SETx assigning to monitor a microcontroller that has both an operational and sleep mode. Microcontroller Window Watchdog Monitoring with Sleep Watchdog Mode The TPS3436-Q1 can utilize high-accuracy voltage monitoring and on-the-fly SETx assigning to monitor a microcontroller that has both an operational and sleep mode.TPS3436-Q1 high-accuracy voltage monitoring and Microcontroller Window Watchdog Monitoring with Sleep Watchdog Mode Microcontroller Window Watchdog Monitoring with Sleep Watchdog Mode Microcontroller Window Watchdog Monitoring with Sleep Watchdog Mode Design Requirements PARAMETER DESIGN REQUIREMENT DESIGN RESULT Window Close Time During Operation Typical tWC of 50 ms during operation Typical tWC of 50ms Window Open Time During Operation Typical tWO of 1.4 s during operation Typical tWO of 1.55 s Window Close Time During Sleep Typical tWC of 50 ms during sleep Typical tWC of 50ms Window Open Time During Sleep Typical tWO of 12 s during sleep Typical tWO of 12.75 s Output Assert Delay Typical tWDO of 200 ms Typical tWDO of 200 ms Output logic voltage Open-drain Open-drain Maximum device current consumption 20 µA 250 nA typical current consumption Design Requirements PARAMETER DESIGN REQUIREMENT DESIGN RESULT Window Close Time During Operation Typical tWC of 50 ms during operation Typical tWC of 50ms Window Open Time During Operation Typical tWO of 1.4 s during operation Typical tWO of 1.55 s Window Close Time During Sleep Typical tWC of 50 ms during sleep Typical tWC of 50ms Window Open Time During Sleep Typical tWO of 12 s during sleep Typical tWO of 12.75 s Output Assert Delay Typical tWDO of 200 ms Typical tWDO of 200 ms Output logic voltage Open-drain Open-drain Maximum device current consumption 20 µA 250 nA typical current consumption PARAMETER DESIGN REQUIREMENT DESIGN RESULT Window Close Time During Operation Typical tWC of 50 ms during operation Typical tWC of 50ms Window Open Time During Operation Typical tWO of 1.4 s during operation Typical tWO of 1.55 s Window Close Time During Sleep Typical tWC of 50 ms during sleep Typical tWC of 50ms Window Open Time During Sleep Typical tWO of 12 s during sleep Typical tWO of 12.75 s Output Assert Delay Typical tWDO of 200 ms Typical tWDO of 200 ms Output logic voltage Open-drain Open-drain Maximum device current consumption 20 µA 250 nA typical current consumption PARAMETER DESIGN REQUIREMENT DESIGN RESULT Window Close Time During Operation Typical tWC of 50 ms during operation Typical tWC of 50ms Window Open Time During Operation Typical tWO of 1.4 s during operation Typical tWO of 1.55 s Window Close Time During Sleep Typical tWC of 50 ms during sleep Typical tWC of 50ms Window Open Time During Sleep Typical tWO of 12 s during sleep Typical tWO of 12.75 s Output Assert Delay Typical tWDO of 200 ms Typical tWDO of 200 ms Output logic voltage Open-drain Open-drain Maximum device current consumption 20 µA 250 nA typical current consumption PARAMETER DESIGN REQUIREMENT DESIGN RESULT Window Close Time During Operation Typical tWC of 50 ms during operation Typical tWC of 50ms Window Open Time During Operation Typical tWO of 1.4 s during operation Typical tWO of 1.55 s Window Close Time During Sleep Typical tWC of 50 ms during sleep Typical tWC of 50ms Window Open Time During Sleep Typical tWO of 12 s during sleep Typical tWO of 12.75 s Output Assert Delay Typical tWDO of 200 ms Typical tWDO of 200 ms Output logic voltage Open-drain Open-drain Maximum device current consumption 20 µA 250 nA typical current consumption PARAMETER DESIGN REQUIREMENT DESIGN RESULT PARAMETER DESIGN REQUIREMENT DESIGN RESULT PARAMETERDESIGN REQUIREMENTDESIGN RESULT Window Close Time During Operation Typical tWC of 50 ms during operation Typical tWC of 50ms Window Open Time During Operation Typical tWO of 1.4 s during operation Typical tWO of 1.55 s Window Close Time During Sleep Typical tWC of 50 ms during sleep Typical tWC of 50ms Window Open Time During Sleep Typical tWO of 12 s during sleep Typical tWO of 12.75 s Output Assert Delay Typical tWDO of 200 ms Typical tWDO of 200 ms Output logic voltage Open-drain Open-drain Maximum device current consumption 20 µA 250 nA typical current consumption Window Close Time During Operation Typical tWC of 50 ms during operation Typical tWC of 50ms Window Close Time During OperationTypical tWC of 50 ms during operationWCTypical tWC of 50msWC Window Open Time During Operation Typical tWO of 1.4 s during operation Typical tWO of 1.55 s Window Open Time During OperationTypical tWO of 1.4 s during operationWOTypical tWO of 1.55 sWO Window Close Time During Sleep Typical tWC of 50 ms during sleep Typical tWC of 50ms Window Close Time During SleepTypical tWC of 50 ms during sleepWCTypical tWC of 50msWC Window Open Time During Sleep Typical tWO of 12 s during sleep Typical tWO of 12.75 s Window Open Time During SleepTypical tWO of 12 s during sleepWOTypical tWO of 12.75 sWO Output Assert Delay Typical tWDO of 200 ms Typical tWDO of 200 ms Output Assert DelayTypical tWDO of 200 msWDOTypical tWDO of 200 msWDO Output logic voltage Open-drain Open-drain Output logic voltageOpen-drainOpen-drain Maximum device current consumption 20 µA 250 nA typical current consumption Maximum device current consumption20 µA250 nA typical current consumption Detailed Design Procedure Determining Window Timings During Operation and Sleep Modes The TPS3436-Q1 allows for precise 10% accurate watchdog timings. This application requires two different window timings in order to maximize power efficiency: one for the microcontroller's operational state and one for its sleep state. To achieve this, the host can reassign the SETx pins when it transitions between states. A window close time, tWC, of 50 ms typical is chosen because of the application's 50 ms typical tWC requirement. The application requires a typical watchdog open time, tWO, of 1.4 s during operation and a tWO of 12 s during sleep. Thus, the possible variant options are narrowed to TPS3436xxFExDDFRQ1. Meeting the Output Assert Delay The TPS3436-Q1 features two options for selecting reset delays: fixed delays and capacitor-programmable delays. The TPS3436-Q1 supports only fixed watchdog timings and fixed output assert delays or programmable watchdog timings and programmable output assert delays. The application requires a 200 ms minimum output assert delay, thus output assert delay option G is used. Because of these requirements and no need for a startup delay, the TPS3436CAFEGDDFRQ1 is used. Calculating the WDO Pullup Resistor The TPS3436-Q1 uses an open-drain configuration for the WDO circuit, as shown in . When the FET is off, the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET attempts to pull the drain to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to ensure that VOL is below its maximum value. To choose the proper pullup resistor, there are three key specifications to keep in mind: the pullup voltage (VPU), the recommended maximum WDO pin current (IRST), and VOL. The maximum VOL is 0.3 V, meaning that the effective resistor divider created must be able to bring the voltage on the reset pin below 0.3 V with IRST kept below 2 mA for VDD ≥ 3 V and 500 μA for VDD = 1.5 V. For this example, with a VPU =VDD = 1.5 V, a resistor must be chosen to keep IRST below 500 μA because this value is the maximum consumption current allowed. To ensure this specification is met, a pullup resistor value of 10 kΩ was selected, which sinks a maximum of 180 μA when WDO is asserted. Open-Drain RESET Configuration Detailed Design Procedure Determining Window Timings During Operation and Sleep Modes The TPS3436-Q1 allows for precise 10% accurate watchdog timings. This application requires two different window timings in order to maximize power efficiency: one for the microcontroller's operational state and one for its sleep state. To achieve this, the host can reassign the SETx pins when it transitions between states. A window close time, tWC, of 50 ms typical is chosen because of the application's 50 ms typical tWC requirement. The application requires a typical watchdog open time, tWO, of 1.4 s during operation and a tWO of 12 s during sleep. Thus, the possible variant options are narrowed to TPS3436xxFExDDFRQ1. Determining Window Timings During Operation and Sleep Modes The TPS3436-Q1 allows for precise 10% accurate watchdog timings. This application requires two different window timings in order to maximize power efficiency: one for the microcontroller's operational state and one for its sleep state. To achieve this, the host can reassign the SETx pins when it transitions between states. A window close time, tWC, of 50 ms typical is chosen because of the application's 50 ms typical tWC requirement. The application requires a typical watchdog open time, tWO, of 1.4 s during operation and a tWO of 12 s during sleep. Thus, the possible variant options are narrowed to TPS3436xxFExDDFRQ1. The TPS3436-Q1 allows for precise 10% accurate watchdog timings. This application requires two different window timings in order to maximize power efficiency: one for the microcontroller's operational state and one for its sleep state. To achieve this, the host can reassign the SETx pins when it transitions between states. A window close time, tWC, of 50 ms typical is chosen because of the application's 50 ms typical tWC requirement. The application requires a typical watchdog open time, tWO, of 1.4 s during operation and a tWO of 12 s during sleep. Thus, the possible variant options are narrowed to TPS3436xxFExDDFRQ1. The TPS3436-Q1 allows for precise 10% accurate watchdog timings. This application requires two different window timings in order to maximize power efficiency: one for the microcontroller's operational state and one for its sleep state. To achieve this, the host can reassign the SETx pins when it transitions between states. A window close time, tWC, of 50 ms typical is chosen because of the application's 50 ms typical tWC requirement. The application requires a typical watchdog open time, tWO, of 1.4 s during operation and a tWO of 12 s during sleep. Thus, the possible variant options are narrowed to TPS3436xxFExDDFRQ1.TPS3436-Q1WCWCWOWOTPS3436xxFExDDFRQ1 Meeting the Output Assert Delay The TPS3436-Q1 features two options for selecting reset delays: fixed delays and capacitor-programmable delays. The TPS3436-Q1 supports only fixed watchdog timings and fixed output assert delays or programmable watchdog timings and programmable output assert delays. The application requires a 200 ms minimum output assert delay, thus output assert delay option G is used. Because of these requirements and no need for a startup delay, the TPS3436CAFEGDDFRQ1 is used. Meeting the Output Assert Delay The TPS3436-Q1 features two options for selecting reset delays: fixed delays and capacitor-programmable delays. The TPS3436-Q1 supports only fixed watchdog timings and fixed output assert delays or programmable watchdog timings and programmable output assert delays. The application requires a 200 ms minimum output assert delay, thus output assert delay option G is used. Because of these requirements and no need for a startup delay, the TPS3436CAFEGDDFRQ1 is used. The TPS3436-Q1 features two options for selecting reset delays: fixed delays and capacitor-programmable delays. The TPS3436-Q1 supports only fixed watchdog timings and fixed output assert delays or programmable watchdog timings and programmable output assert delays. The application requires a 200 ms minimum output assert delay, thus output assert delay option G is used. Because of these requirements and no need for a startup delay, the TPS3436CAFEGDDFRQ1 is used. The TPS3436-Q1 features two options for selecting reset delays: fixed delays and capacitor-programmable delays. The TPS3436-Q1 supports only fixed watchdog timings and fixed output assert delays or programmable watchdog timings and programmable output assert delays. The application requires a 200 ms minimum output assert delay, thus output assert delay option G is used. Because of these requirements and no need for a startup delay, the TPS3436CAFEGDDFRQ1 is used.TPS3436-Q1TPS3436-Q1TPS3436CAFEGDDFRQ1 Calculating the WDO Pullup Resistor The TPS3436-Q1 uses an open-drain configuration for the WDO circuit, as shown in . When the FET is off, the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET attempts to pull the drain to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to ensure that VOL is below its maximum value. To choose the proper pullup resistor, there are three key specifications to keep in mind: the pullup voltage (VPU), the recommended maximum WDO pin current (IRST), and VOL. The maximum VOL is 0.3 V, meaning that the effective resistor divider created must be able to bring the voltage on the reset pin below 0.3 V with IRST kept below 2 mA for VDD ≥ 3 V and 500 μA for VDD = 1.5 V. For this example, with a VPU =VDD = 1.5 V, a resistor must be chosen to keep IRST below 500 μA because this value is the maximum consumption current allowed. To ensure this specification is met, a pullup resistor value of 10 kΩ was selected, which sinks a maximum of 180 μA when WDO is asserted. Open-Drain RESET Configuration Calculating the WDO Pullup ResistorWDO The TPS3436-Q1 uses an open-drain configuration for the WDO circuit, as shown in . When the FET is off, the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET attempts to pull the drain to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to ensure that VOL is below its maximum value. To choose the proper pullup resistor, there are three key specifications to keep in mind: the pullup voltage (VPU), the recommended maximum WDO pin current (IRST), and VOL. The maximum VOL is 0.3 V, meaning that the effective resistor divider created must be able to bring the voltage on the reset pin below 0.3 V with IRST kept below 2 mA for VDD ≥ 3 V and 500 μA for VDD = 1.5 V. For this example, with a VPU =VDD = 1.5 V, a resistor must be chosen to keep IRST below 500 μA because this value is the maximum consumption current allowed. To ensure this specification is met, a pullup resistor value of 10 kΩ was selected, which sinks a maximum of 180 μA when WDO is asserted. Open-Drain RESET Configuration The TPS3436-Q1 uses an open-drain configuration for the WDO circuit, as shown in . When the FET is off, the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET attempts to pull the drain to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to ensure that VOL is below its maximum value. To choose the proper pullup resistor, there are three key specifications to keep in mind: the pullup voltage (VPU), the recommended maximum WDO pin current (IRST), and VOL. The maximum VOL is 0.3 V, meaning that the effective resistor divider created must be able to bring the voltage on the reset pin below 0.3 V with IRST kept below 2 mA for VDD ≥ 3 V and 500 μA for VDD = 1.5 V. For this example, with a VPU =VDD = 1.5 V, a resistor must be chosen to keep IRST below 500 μA because this value is the maximum consumption current allowed. To ensure this specification is met, a pullup resistor value of 10 kΩ was selected, which sinks a maximum of 180 μA when WDO is asserted. Open-Drain RESET Configuration The TPS3436-Q1 uses an open-drain configuration for the WDO circuit, as shown in . When the FET is off, the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET attempts to pull the drain to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to ensure that VOL is below its maximum value. To choose the proper pullup resistor, there are three key specifications to keep in mind: the pullup voltage (VPU), the recommended maximum WDO pin current (IRST), and VOL. The maximum VOL is 0.3 V, meaning that the effective resistor divider created must be able to bring the voltage on the reset pin below 0.3 V with IRST kept below 2 mA for VDD ≥ 3 V and 500 μA for VDD = 1.5 V. For this example, with a VPU =VDD = 1.5 V, a resistor must be chosen to keep IRST below 500 μA because this value is the maximum consumption current allowed. To ensure this specification is met, a pullup resistor value of 10 kΩ was selected, which sinks a maximum of 180 μA when WDO is asserted. TPS3436-Q1WDOOLPUWDORSTOLOLRSTDDDDPUDDRSTWDO Open-Drain RESET Configuration Open-Drain RESET ConfigurationRESET Power Supply Recommendations This device is designed to operate from an input supply with a voltage range between 1.04 V and 6 V. An input supply capacitor is not required for this device; however, if the input supply is noisy, then good analog practice is to place a 0.1-µF capacitor between the VDD pin and the GND pin. Power Supply Recommendations This device is designed to operate from an input supply with a voltage range between 1.04 V and 6 V. An input supply capacitor is not required for this device; however, if the input supply is noisy, then good analog practice is to place a 0.1-µF capacitor between the VDD pin and the GND pin. This device is designed to operate from an input supply with a voltage range between 1.04 V and 6 V. An input supply capacitor is not required for this device; however, if the input supply is noisy, then good analog practice is to place a 0.1-µF capacitor between the VDD pin and the GND pin. This device is designed to operate from an input supply with a voltage range between 1.04 V and 6 V. An input supply capacitor is not required for this device; however, if the input supply is noisy, then good analog practice is to place a 0.1-µF capacitor between the VDD pin and the GND pin. Layout Layout Guidelines Make sure that the connection to the VDD pin is low impedance. Good analog design practice recommends placing a 0.1-µF ceramic capacitor as near as possible to the VDD pin. If a capacitor is not connected to the CRST pin, then minimize parasitic capacitance on this pin so the WDO delay time is not adversely affected. Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a 0.1-µF ceramic capacitor as near as possible to the VDD pin. Place CCRST capacitor as close as possible to the CRST pin. Place CCWD capacitor as close as possible to the CWD pin. Place the pullup resistor on the WDO pin as close to the pin as possible. Layout Example Typical Layout for the Pinout C of TPS3436-Q1 Layout Layout Guidelines Make sure that the connection to the VDD pin is low impedance. Good analog design practice recommends placing a 0.1-µF ceramic capacitor as near as possible to the VDD pin. If a capacitor is not connected to the CRST pin, then minimize parasitic capacitance on this pin so the WDO delay time is not adversely affected. Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a 0.1-µF ceramic capacitor as near as possible to the VDD pin. Place CCRST capacitor as close as possible to the CRST pin. Place CCWD capacitor as close as possible to the CWD pin. Place the pullup resistor on the WDO pin as close to the pin as possible. Layout Guidelines Make sure that the connection to the VDD pin is low impedance. Good analog design practice recommends placing a 0.1-µF ceramic capacitor as near as possible to the VDD pin. If a capacitor is not connected to the CRST pin, then minimize parasitic capacitance on this pin so the WDO delay time is not adversely affected. Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a 0.1-µF ceramic capacitor as near as possible to the VDD pin. Place CCRST capacitor as close as possible to the CRST pin. Place CCWD capacitor as close as possible to the CWD pin. Place the pullup resistor on the WDO pin as close to the pin as possible. Make sure that the connection to the VDD pin is low impedance. Good analog design practice recommends placing a 0.1-µF ceramic capacitor as near as possible to the VDD pin. If a capacitor is not connected to the CRST pin, then minimize parasitic capacitance on this pin so the WDO delay time is not adversely affected. Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a 0.1-µF ceramic capacitor as near as possible to the VDD pin. Place CCRST capacitor as close as possible to the CRST pin. Place CCWD capacitor as close as possible to the CWD pin. Place the pullup resistor on the WDO pin as close to the pin as possible. Make sure that the connection to the VDD pin is low impedance. Good analog design practice recommends placing a 0.1-µF ceramic capacitor as near as possible to the VDD pin. If a capacitor is not connected to the CRST pin, then minimize parasitic capacitance on this pin so the WDO delay time is not adversely affected. Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a 0.1-µF ceramic capacitor as near as possible to the VDD pin. Place CCRST capacitor as close as possible to the CRST pin. Place CCWD capacitor as close as possible to the CWD pin. Place the pullup resistor on the WDO pin as close to the pin as possible. WDO WDO Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a 0.1-µF ceramic capacitor as near as possible to the VDD pin. Place CCRST capacitor as close as possible to the CRST pin. Place CCWD capacitor as close as possible to the CWD pin. Place the pullup resistor on the WDO pin as close to the pin as possible. Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a 0.1-µF ceramic capacitor as near as possible to the VDD pin.Place CCRST capacitor as close as possible to the CRST pin.CRSTPlace CCWD capacitor as close as possible to the CWD pin.CWDPlace the pullup resistor on the WDO pin as close to the pin as possible. WDO WDO Layout Example Typical Layout for the Pinout C of TPS3436-Q1 Layout Example Typical Layout for the Pinout C of TPS3436-Q1 Typical Layout for the Pinout C of TPS3436-Q1 Typical Layout for the Pinout C of TPS3436-Q1 Typical Layout for the Pinout C of TPS3436-Q1 TPS3436-Q1 Device and Documentation Support Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. Trademarks Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Device and Documentation Support Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.ti.comSubscribe to updates Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. TI E2E support forumsTI E2ELinked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.Terms of Use Trademarks Trademarks Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary TI GlossaryThis glossary lists and explains terms, acronyms, and definitions. Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 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GUID-20210706-CA0I-PSXG-WGJK-QZH14WLL6LMK-low.svg Figure 5-1 Device Naming Nomenclature

TPS3436-Q1 belongs to family of pin compatible devices offering different feature sets as highlighted in Table 5-1.

Table 5-1 Pin Compatible Device Families
DEVICEVOLTAGE SUPERVISORTYPE OF WATCHDOG
TPS35-Q1YesTimeout
TPS36-Q1YesWindow
TPS3435-Q1NoTimeout
TPS3436-Q1NoWindow