SLVSGF1A october   2022  – june 2023 TPS3436-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Timing Diagrams
    9. 7.9 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Window Watchdog Timer
        1. 8.3.1.1 tWC (Close Window) Timer
        2. 8.3.1.2 tWO (Open Window) Timer
        3. 8.3.1.3 Watchdog Enable Disable Operation
        4. 8.3.1.4 tSD Watchdog Start Up Delay
        5. 8.3.1.5 SET Pin Behavior
      2. 8.3.2 Manual RESET
      3. 8.3.3 WDO Output
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Output Assert Delay
        1. 9.1.1.1 Factory-Programmed Output Assert Delay Timing
        2. 9.1.1.2 Adjustable Capacitor Timing
      2. 9.1.2 Watchdog Window Functionality
        1. 9.1.2.1 Factory-Programmed Timing Options
        2. 9.1.2.2 Adjustable Capacitor Timing
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1: Monitoring a Microcontroller Watchdog During Operational and Sleep Modes
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Determining Window Timings During Operation and Sleep Modes
          2. 9.2.1.2.2 Meeting the Output Assert Delay
          3. 9.2.1.2.3 Calculating the WDO Pullup Resistor
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.7 Switching Characteristics

At 1.04 V ≤ VDD ≤ 6 V, MR = Open, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output RESET / WDO load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tSTRT Startup delay (1) CCRST pin = Open or NC
 		 500 µs
tSD Watchdog startup delay Orderable part number TPS3436xA, TPS343xG 0 ms
Orderable part number TPS3436xB, TPS3436xH 180 200 220
Orderable part number TPS3436xC, TPS3436xI 450 500 550
Orderable part number TPS3436xD, TPS3436xJ 0.9 1 1.1 s
Orderable part number TPS3436xE, TPS3436xK 4.5 5 5.5
Orderable part number TPS3436xF, TPS3436xL 9 10 11
tWDO Watchdog assert time delay Orderable part number TPS3436xxxxB 1.6 2 2.4 ms
Orderable part number TPS3436xxxxC 9 10 11 ms
Orderable part number TPS3436xxxxD 22.5 25 27.5 ms
Orderable part number TPS3436xxxxE 45 50 55 ms
Orderable part number TPS3436xxxxF 90 100 110 ms
Orderable part number TPS3436xxxxG 180 200 220 ms
Orderable part number TPS3436xxxxH 0.9 1 1.1 s
Orderable part number TPS3436xxxxI 9 10 11 s
tMR_WDO Propagation delay from MR low to WDO assertion VDD ≥ 1.25 V,
MR = VMR_H to VMR_L		 100 ns
(1) Specified by design parameter.