SLVSGE8B November   2022  – August 2024 TPS35-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Voltage Supervisor
      2. 7.3.2 Timeout Watchdog Timer
        1. 7.3.2.1 tWD Timer
        2. 7.3.2.2 Watchdog Enable Disable Operation
        3. 7.3.2.3 tSD Watchdog Start Up Delay
        4. 7.3.2.4 SET Pin Behavior
      3. 7.3.3 Manual RESET
      4. 7.3.4 RESET and WDO Output
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 CRST Delay
        1. 8.1.1.1 Factory-Programmed watchdog Timing
        2. 8.1.1.2 Adjustable Capacitor Timing
      2. 8.1.2 Watchdog Timer Functionality
        1. 8.1.2.1 Factory-Programmed watchdog Timing
        2. 8.1.2.2 Adjustable Capacitor Timings
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1: Monitoring a Microcontroller Supply Voltage and Watchdog Timer
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Setting the Voltage Threshold
          2. 8.2.1.2.2 Meeting the Watchdog Timeout Period
          3. 8.2.1.2.3 Setting the Reset Delay
          4. 8.2.1.2.4 Setting the Startup Delay and Output Topology
          5. 8.2.1.2.5 Calculating the RESET Pullup Resistor
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
8.2.1.2.5 Calculating the RESET Pullup Resistor

The TPS35-Q1 uses an open-drain configuration for the RESET output, as shown in Figure 8-2. When the FET is off, the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET pulls the output to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to make sure that VOL is below the maximum value. To choose the proper pullup resistor, there are three key specifications to keep in mind: the pullup voltage (VPU), the recommended maximum RESET pin current (IRST), and VOL. The maximum VOL is 0.3V, meaning that the effective resistor divider created must be able to bring the voltage on the reset pin below 0.3V with IRST kept below 2mA for VDD ≥ 3V and 500μA for VDD = 1.5V. For this example, with a VPU =VDD = 1.5V, a resistor must be chosen to keep IRST below 500μA because this value is the maximum consumption current allowed. To make sure this specification is met, a pullup resistor value of 10kΩ was selected, which sinks a maximum of 180μA when RESET is asserted.

TPS35-Q1 Open-Drain RESET Configuration Figure 8-2 Open-Drain RESET Configuration