SNVSCF5A June   2023  – December 2023 TPS35

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics
    9. 6.9  Timing Diagrams
    10. 6.10 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Voltage Supervisor
      2. 7.3.2 Timeout Watchdog Timer
        1. 7.3.2.1 tWD Timer
        2. 7.3.2.2 Watchdog Enable Disable Operation
        3. 7.3.2.3 tSD Watchdog Start Up Delay
        4. 7.3.2.4 SET Pin Behavior
      3. 7.3.3 Manual RESET
      4. 7.3.4 RESET and WDO Output
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Output Assert Delay
        1. 8.1.1.1 Factory-Programmed Output Assert Delay Timing
        2. 8.1.1.2 Adjustable Capacitor Timing
      2. 8.1.2 Watchdog Timer Functionality
        1. 8.1.2.1 Factory-Programmed Timing Options
        2. 8.1.2.2 Adjustable Capacitor Timing
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1: Monitoring a Microcontroller Supply Voltage and Watchdog Timer
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Setting the Voltage Threshold
          2. 8.2.1.2.2 Meeting the Watchdog Timeout Period
          3. 8.2.1.2.3 Setting the Reset Delay
          4. 8.2.1.2.4 Setting the Startup Delay and Output Topology
          5. 8.2.1.2.5 Calculating the RESET Pullup Resistor
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.8 Switching Characteristics

At 1.04 V ≤ VDD ≤ 6 V, MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output RESET / WDO load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tSTRT Startup delay(2)
 		 500 µs
tP_HL RESET detect delay for VDD falling below VIT– VDD : (VIT+ + 10%) to (VIT– – 10%)(1) 30 50 µs
tSD Watchdog startup delay Orderable part number TPS35xA, TPS35xG 0 ms
Orderable part number TPS35xB, TPS35xH 180 200 220
Orderable part number TPS35xC, TPS35xI 450 500 550
Orderable part number TPS35xD, TPS35xJ 0.9 1 1.1 s
Orderable part number TPS35xE, TPS35xK 4.5 5 5.5
Orderable part number TPS35xF, TPS35xL 9 10 11
tD Reset time delay (3) Orderable part number TPS35xxxxxxB 1.6 2 2.4 ms
Orderable part number TPS35xxxxxxC 9 10 11 ms
Orderable part number TPS35xxxxxxD 22.5 25 27.5 ms
Orderable part number TPS35xxxxxxE 45 50 55 ms
Orderable part number TPS35xxxxxxF 90 100 110 ms
Orderable part number TPS35xxxxxxG 180 200 220 ms
Orderable part number TPS35xxxxxxH 0.9 1 1.1 s
Orderable part number TPS35xxxxxxI 9 10 11 s
tWDO Watchdog timeout delay tD s
tMR_RES Propagation delay from MR low to reset assertion VDD ≥ VIT– + 0.2 V,
MR = VMR_H to VMR_L		 100 ns
tMR_tD Delay from MR  release to reset deassert VDD = 3.3 V,
MR = VMR_L to VMR_H  		 tD s
(1) tP_HL measured from threshold trip point (VIT–) to RESET assert. VIT+ = VIT– + VHYS
(2) Specified by design parameter. When VDD starts from less than the specified minimum VDD and then exceeds VIT+, reset is deasserted after the startup delay (tSTRT) + tD delay.
(3) VDD voltage transitions from (VIT– - 10%) to (VIT– + 10%)