SLVSGE9A november   2022  – april 2023 TPS36-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Timing Diagrams
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Voltage Supervisor
      2. 8.3.2 Window Watchdog Timer
        1. 8.3.2.1 tWC (Close Window) Timer
        2. 8.3.2.2 tWO (Open Window) Timer
        3. 8.3.2.3 Watchdog Enable Disable Operation
        4. 8.3.2.4 tSD Watchdog Start Up Delay
        5. 8.3.2.5 SET Pin Behavior
      3. 8.3.3 Manual RESET
      4. 8.3.4 RESET and WDO Output
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 CRST Delay
        1. 9.1.1.1 Factory-Programmed Reset Delay Timing
        2. 9.1.1.2 Adjustable Capacitor Timing
      2. 9.1.2 Watchdog Window Functionality
        1. 9.1.2.1 Factory-Programmed watchdog Timing
        2. 9.1.2.2 Adjustable Capacitor Timing
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1: Monitoring Microcontroller Supply and Watchdog During Operational and Sleep Modes
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Setting Voltage Threshold
          2. 9.2.1.2.2 Determining Window Timings During Operation and Sleep Modes
          3. 9.2.1.2.3 Meeting the Minimum Reset Delay
          4. 9.2.1.2.4 Setting the Watchdog Window
          5. 9.2.1.2.5 Calculating the RESET Pullup Resistor
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.2.5 SET Pin Behavior

The TPS36-Q1 offers one or two SET pins based on the pinout option selected. SET pins offer flexibility to the user to program the tWO timer on the fly to meet various application requirements. Typical use cases where SET pin can be used are

  • Use wide open window timer when host is in sleep mode, change to small timeout operation when host is operational. Watchdog can be used to wake up the host after long duration to perform the application related activities before going back to sleep.
  • Change to wide open window timer when performing system critical tasks to ensure watchdog does not interrupt the critical task. Change timer to application specified interval after the critical task is complete.

The tWO timer value for the device is combination of tWC timer selection based on the CWD pin or fixed timer value along with SET pin logic level. The tWC timer value is decided based on the Watchdog Close Time selector in the Section 5 section. The SET pin logic level is decoded during the device power up. The SET pin value can be changed any time during the operation. SETx pin change which leads to change of watchdog timer value or enable disable state, terminates the ongoing watchdog frame immediately. SETx pins can be updated when WDO or RESET output is asserted as well. The updated tWO timer value will be applied after output is deasserted and the tSD timer is over or terminated.

For a pinout which offers only SET0 pin to the user, the tWO ratio value is decided based on the Watchdog Open Time Ratio selector field in the orderable part number. Refer Section 5 for available options. Table 8-4 showcases an example of the tWO values for different SET0 logic levels when using Watchdog Close Time setting as option D = 10 msec.

Table 8-4 tWO Values with SET0 Pin Only (Pin Configuration A)
Watchdog Open Time Ratio Selection tWO
SET0 = 0 SET0 = 1
A 10 msec 30 msec
B 30 msec 70 msec
C 70 msec 150 msec
D 150 msec 310 msec
E 310 msec 630 msec
F 630 msec 1270 msec

Pinout which offer both SET0 & SET1 pins to the user, the tWO ratio value is decided based on the Watchdog Open Time Ratio selector field in the orderable part number. Refer Section 5 for available options. Two SETx pins offer 3 different time scaling options. The SET[1:0] = 0b'01 combination disables the watchdog operation. Table 8-5 showcases an example of the tWO values for different SET[1:0] logic levels when using Watchdog Close Time setting as option G = 100 msec. The package pin out selected does not offer WD-EN pin.

Table 8-5 tWO Values with SET0 & SET1 Pins, WD-EN Pin Not Available (Pin Configuration B)
Watchdog Open Time Ratio selection tWO
SET[1:0] = 0b'00 SET[1:0] = 0b'01 SET[1:0] = 0b'10 SET[1:0] = 0b'11
A100 msecWatchdog disable300 msec1500 msec
B300 msecWatchdog disable700 msec3100 msec
C700 msecWatchdog disable1500 msec6300 msec
D1500 msecWatchdog disable3100 msec12700 msec
E3100 msecWatchdog disable6300 msec25500 msec
F6300 msecWatchdog disable12700 msec51100 msec
  1. Example for Watchdog Close Time setting = 100 msec.

Selected pinout option can offer WD-EN pin along with SET[1:0] pins (Pin Configuration C, D). With this pinout, the WD-EN pin controls watchdog enable and disable operation. The SET[1:0] = 0b'01 combination operates as SET[1:0] = 0b'00.

Ensure the tWO value with SETx ratio does not exceed 640 sec. If a selection of close window timer and ratio results in tWO > 640 sec, the timer value will be restricted to 640 sec.

Figure 8-9 to Figure 8-11 show the timing behavior with respect to SETx status changes.

GUID-20220724-SS0I-NZXJ-HR80-WKNM0MHPSSQC-low.svgFigure 8-9 Watchdog Behavior with SETx Pin Status
GUID-20221026-SS0I-00WX-GQGF-SMMCKJRM0GCJ-low.svgFigure 8-10 Watchdog Operation with 2 SET Pins
GUID-20220724-SS0I-LX9Z-G2MG-NDBWCC16JT6K-low.svgFigure 8-11 Watchdog Operation with 1 SET Pin