SLVSGE9A november   2022  – april 2023 TPS36-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Timing Diagrams
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Voltage Supervisor
      2. 8.3.2 Window Watchdog Timer
        1. 8.3.2.1 tWC (Close Window) Timer
        2. 8.3.2.2 tWO (Open Window) Timer
        3. 8.3.2.3 Watchdog Enable Disable Operation
        4. 8.3.2.4 tSD Watchdog Start Up Delay
        5. 8.3.2.5 SET Pin Behavior
      3. 8.3.3 Manual RESET
      4. 8.3.4 RESET and WDO Output
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 CRST Delay
        1. 9.1.1.1 Factory-Programmed Reset Delay Timing
        2. 9.1.1.2 Adjustable Capacitor Timing
      2. 9.1.2 Watchdog Window Functionality
        1. 9.1.2.1 Factory-Programmed watchdog Timing
        2. 9.1.2.2 Adjustable Capacitor Timing
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1: Monitoring Microcontroller Supply and Watchdog During Operational and Sleep Modes
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Setting Voltage Threshold
          2. 9.2.1.2.2 Determining Window Timings During Operation and Sleep Modes
          3. 9.2.1.2.3 Meeting the Minimum Reset Delay
          4. 9.2.1.2.4 Setting the Watchdog Window
          5. 9.2.1.2.5 Calculating the RESET Pullup Resistor
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.2.1 tWC (Close Window) Timer

The window watchdog frame consists of two sub frames tWC followed by tWO. The host is not expected to drive valid WDI transition during tWC time. A valid WDI transition during tWC frame results in early fault condition and the WDO output is asserted. RESET output is asserted if pinout does not offer independent WDO output. The tWC timer for TPS36-Q1 can be set using an external capacitor connected between CWD pin and GND pin. This feature is available with pinout options A or B. Applications which are space constrained or need timer values which meet offered timer options, can benefit when using pinout options C or D. The TPS36-Q1 offers multiple fixed timer options ranging from 1 msec up-to 100 sec.

The TPS36-Q1 when using capacitance based timer, senses the capacitance value during the power up or after a RESET event. The capacitor is charged and discharged with known internal current source for one cycle to sense the capacitance value. The sensed value is used to arrive at tWC timer for the watchdog operation. This unique implementation helps reduce the continuous charge and discharge current for the capacitor, thus reducing overall current consumption. Continuous charge and discharge of capacitance creates wider dead time (no watchdog monitor functionality) when capacitor is discharging. The dead time is higher for high value of capacitance. The unique implementation of TPS36-Q1 helps avoid the dead time as the capacitance is not continuously charging or discharging under normal operation. Ensure CCWD is < 200 x CCRST for accurate calibration of capacitance. The close time window is decided based on SETx pin combination and the CWD capacitance. Table 8-1 to Table 8-3 highlights the relationship between tWC in second and CWD capacitance in farad. The tWC timer is 20% accurate for an ideal capacitor. Accuracy of the capacitance will have additional impact on the tWC time. Ensure the capacitance meets the recommended operating range. Capacitance outside the recommended range can lead to incorrect operation of the device.

Table 8-1 tWC Equation 1 SET Pin (Pin Configuration A)
SET pin valueEquation
0tWC (sec) = 79.2 x 106 x CCWD (F)
1tWC (sec) = 39.6 x 106 x CCWD (F)
Table 8-2 tWC Equation 2 SET Pin, WD-EN = 1 (Pin Configuration C, D)
SET Pin ValueEquation
00tWC (sec) = 79.2 x 106 x CCWD (F)
01tWC (sec) = 79.2 x 106 x CCWD (F)
10tWC (sec) = 39.6 x 106 x CCWD (F)
11tWC (sec) = 9.9 x 106 x CCWD (F)
Table 8-3 tWC Equation 2 SET Pin, WD-EN Not Available (Pin Configuration B)
SET Pin Value Equation
00 tWC (sec) = 79.2 x 106 x CCWD (F)
01 Watchdog disabled
10 tWC (sec) = 39.6 x 106 x CCWD (F)
11 tWC (sec) = 9.9 x 106 x CCWD (F)

The TPS36-Q1 also offers wide selection of high accuracy fixed tWC timer options starting from 1 msec to 100 sec including various industry standard values. The TPS36-Q1 fixed time options are ±10% accurate for tWC ≥ 10 msec. For tWC < 10 msec, the accuracy is ±20%. tWC value relevant to application can be identified from the orderable part number. Refer Section 5 to identify mapping of orderable part number to tWC value.