SLVSGE9A november   2022  – april 2023 TPS36-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Timing Diagrams
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Voltage Supervisor
      2. 8.3.2 Window Watchdog Timer
        1. 8.3.2.1 tWC (Close Window) Timer
        2. 8.3.2.2 tWO (Open Window) Timer
        3. 8.3.2.3 Watchdog Enable Disable Operation
        4. 8.3.2.4 tSD Watchdog Start Up Delay
        5. 8.3.2.5 SET Pin Behavior
      3. 8.3.3 Manual RESET
      4. 8.3.4 RESET and WDO Output
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 CRST Delay
        1. 9.1.1.1 Factory-Programmed Reset Delay Timing
        2. 9.1.1.2 Adjustable Capacitor Timing
      2. 9.1.2 Watchdog Window Functionality
        1. 9.1.2.1 Factory-Programmed watchdog Timing
        2. 9.1.2.2 Adjustable Capacitor Timing
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1: Monitoring Microcontroller Supply and Watchdog During Operational and Sleep Modes
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Setting Voltage Threshold
          2. 9.2.1.2.2 Determining Window Timings During Operation and Sleep Modes
          3. 9.2.1.2.3 Meeting the Minimum Reset Delay
          4. 9.2.1.2.4 Setting the Watchdog Window
          5. 9.2.1.2.5 Calculating the RESET Pullup Resistor
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4 Thermal Information

THERMAL METRIC(1) TPS36-Q1 UNIT
DDF (SOT23-8)
8 PINS
RθJA Junction-to-ambient thermal resistance 175.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 94.7 °C/W
RθJB Junction-to-board thermal resistance 92.4 °C/W
ψJT Junction-to-top characterization parameter 8.4 °C/W
ψJB Junction-to-board characterization parameter 91.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.