SLVSGE9A november   2022  – april 2023 TPS36-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Timing Diagrams
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Voltage Supervisor
      2. 8.3.2 Window Watchdog Timer
        1. 8.3.2.1 tWC (Close Window) Timer
        2. 8.3.2.2 tWO (Open Window) Timer
        3. 8.3.2.3 Watchdog Enable Disable Operation
        4. 8.3.2.4 tSD Watchdog Start Up Delay
        5. 8.3.2.5 SET Pin Behavior
      3. 8.3.3 Manual RESET
      4. 8.3.4 RESET and WDO Output
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 CRST Delay
        1. 9.1.1.1 Factory-Programmed Reset Delay Timing
        2. 9.1.1.2 Adjustable Capacitor Timing
      2. 9.1.2 Watchdog Window Functionality
        1. 9.1.2.1 Factory-Programmed watchdog Timing
        2. 9.1.2.2 Adjustable Capacitor Timing
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1: Monitoring Microcontroller Supply and Watchdog During Operational and Sleep Modes
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Setting Voltage Threshold
          2. 9.2.1.2.2 Determining Window Timings During Operation and Sleep Modes
          3. 9.2.1.2.3 Meeting the Minimum Reset Delay
          4. 9.2.1.2.4 Setting the Watchdog Window
          5. 9.2.1.2.5 Calculating the RESET Pullup Resistor
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

At 1.04 V ≤ VDD ≤ 6 V, MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
COMMON PARAMETERS
VDD Input supply voltage Active LOW output 1.04 6 V
VIT– Negative-going input threshold accuracy (1) VIT– = 1.05 V to 1.95 V –1.4 ±0.5 1.4 %
VIT– = 2.0 V to 5.4 V –1.2 ±0.5 1.2
VHYS Hysteresis VIT– pin VIT– = 1.05 V to 5.4 V 3 5 7 %
IDD Supply current into VDD pin (2) VDD = 2 V
VIT– = 1.05 V to 1.95 V		 TA = –40℃ to 85℃  0.25 0.8 µA
0.25 3
VDD = 6 V
VIT– = 1.05 V to 5.4 V		 TA = –40℃ to 85℃  0.25 0.8
0.25 3
VIL Low level input voltage WD–EN, WDI, SETx, MR(3) 0.3VDD V
VIH High level input voltage WD–EN, WDI, SETx, MR(3) 0.7VDD V
RMR Manual reset internal pull-up resistance 100 kΩ
RESET / WDO (Open-drain active-low)
VOL Low level output voltage
 		 VDD =1.5 V, 1.55 V ≤ VIT– ≤ 3.35 V
IOUT(Sink) = 500 µA		 300 mV
VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.4 V
IOUT(Sink) = 2 mA		 300
Ilkg(OD) Open-Drain output leakage current VDD = VPULLUP = 6V
TA = –40℃ to 85℃		 10 30 nA
VDD = VPULLUP = 6V 10 120 nA
RESET / WDO (Push-pull active-low)
VPOR Power on RESET voltage (5) VOL(max) = 300 mV
IOUT(Sink) = 15 µA		 900 mV
VOL Low level output voltage
 		 VDD = 0.9 V, 1.05 V ≤ VIT– ≤ 1.5 V
IOUT(Sink) = 15 µA		 300 mV
VDD = 1.5 V, 1.55 V ≤ VIT– ≤ 3.35 V
IOUT(Sink) = 500 µA		 300
VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.4 V
IOUT(Sink) = 2 mA		 300
VOH High level output voltage
 		 VDD = 1.8 V, 1.05 V ≤ VIT– ≤ 1.4 V
IOUT(Source) = 500 µA		 0.8VDD V
VDD = 3.3 V, 1.45 V ≤ VIT– ≤ 3.0 V
IOUT(Source) = 500 µA		 0.8VDD
VDD = 6 V, 3.05 V ≤ VIT– ≤ 5.4 V
IOUT(Source) = 2 mA		 0.8VDD
(1) VIT– threshold voltage range from 1.05 V to 5.4 V in 50 mV steps.
(2) If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR.
(3) VPOR is the minimum VDD voltage level for a controlled output state