SNVSBJ1E october   2020  – august 2023 TPS37

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (VDD)
        1. 8.3.1.1 Undervoltage Lockout (VPOR < VDD < UVLO)
        2. 8.3.1.2 Power-On Reset (VDD < VPOR )
      2. 8.3.2 SENSE
        1. 8.3.2.1 SENSE Hysteresis
      3. 8.3.3 Output Logic Configurations
        1. 8.3.3.1 Open-Drain
        2. 8.3.3.2 Push-Pull
        3. 8.3.3.3 Active-High (RESET)
        4. 8.3.3.4 Active-Low (RESET)
      4. 8.3.4 User-Programmable Reset Time Delay
        1. 8.3.4.1 Reset Time Delay Configuration
      5. 8.3.5 User-Programmable Sense Delay
        1. 8.3.5.1 Sense Time Delay Configuration
      6. 8.3.6 Manual RESET (CTR1 / MR) and (CTR2 / MR) Input
  10. 9 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Adjustable Voltage Thresholds
      1. 10.1.1 Application Curves
    2. 10.2 Application Information
      1. 10.2.1 Typical Application
        1. 10.2.1.1 Design 1: High Voltage – Fast AC Signal Monitoring For Power Fault Detection
          1. 10.2.1.1.1 Design Requirements
          2. 10.2.1.1.2 Detailed Design Procedure
    3. 10.3 Power Supply Recommendations
      1. 10.3.1 Power Dissipation and Device Operation
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
      3. 10.4.3 Creepage Distance
  12. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.1 Adjustable Voltage Thresholds

Equation 7 illustrates an example of how to adjust the voltage threshold with external resistor dividers. The resistors can be calculated depending on the desired voltage threshold and device part number. TI recommends using the 0.8 V voltage threshold device when using an adjustable voltage variant. This variant bypasses the internal resistor ladder.

For example, consider a 12 V rail being monitored VMON for undervoltage (UV) using channel 2 of the TPS37A010122DSKR variant. Using Equation 7 and shown in Figure 10-1, R1 is the top resistor of the resistor divider that is between VMON and VSENSE2, R2 is the bottom resistor that is between VSENSE2 and GND, VMON is the voltage rail that is being monitored and VSENSE2 is the input threshold voltage. The monitored UV threshold, denoted as VMON-, where the device will assert a reset signal occurs when VSENSE2 = VIT-(UV) or, for this example, VMON- = 10.8V which is 90% from 12 V. Using Equation 7 and assuming R2 = 10kΩ, R1 can be calculated shown in Equation 8 where IR1 is represented in Equation 9:

Equation 7. VSENSE2 = VMON- × (R2 ÷ (R1 + R2))
Equation 8. R1 = (VMON- - VSENSE2) ÷ IR1
Equation 9. IR1 = IR2 = VSENSE2 ÷ R2

Substituting Equation 9 into Equation 8 and solving for R1 in Equation 7, R1 = 125kΩ. The TPS37A010122DSKR is typically meant to monitor a 0.8 V rail with ±2% voltage threshold hysteresis. For the reset signal to become deasserted, VMON would need to go above VIT- + VHYS. For this example, VMON = 11.016 V when the reset signal becomes deasserted.

There are inaccuracies that must be taken into consideration while adjusting voltage thresholds. Aside from the tolerance of the resistor divider, there is an internal resistance of the SENSE pin that may affect the accuracy of the resistor divider. Although expected to be very high impedance, users are recommended to calculate the values for the design specifications. The internal SENSE resistance RSENSE can be calculated by the SENSE voltage VSENSE divided by the SENSE current ISENSE as shown in Equation 11. VSENSE can be calculated using Equation 7 depending on the resistor divider and monitored voltage. ISENSE can be calculated using Equation 10.

Equation 10. ISENSE = [(VMON - VSENSE) ÷ R1] - (VSENSE ÷ R2)
Equation 11. RSENSE = VSENSE ÷ ISENSE
GUID-20210529-CA0I-KTLT-LJHL-KTT2S9RFCS04-low.svg Figure 10-1 Adjustable Voltage Threshold with External Resistor Dividers