SNVSBJ1E october   2020  – august 2023 TPS37

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (VDD)
        1. 8.3.1.1 Undervoltage Lockout (VPOR < VDD < UVLO)
        2. 8.3.1.2 Power-On Reset (VDD < VPOR )
      2. 8.3.2 SENSE
        1. 8.3.2.1 SENSE Hysteresis
      3. 8.3.3 Output Logic Configurations
        1. 8.3.3.1 Open-Drain
        2. 8.3.3.2 Push-Pull
        3. 8.3.3.3 Active-High (RESET)
        4. 8.3.3.4 Active-Low (RESET)
      4. 8.3.4 User-Programmable Reset Time Delay
        1. 8.3.4.1 Reset Time Delay Configuration
      5. 8.3.5 User-Programmable Sense Delay
        1. 8.3.5.1 Sense Time Delay Configuration
      6. 8.3.6 Manual RESET (CTR1 / MR) and (CTR2 / MR) Input
  10. 9 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Adjustable Voltage Thresholds
      1. 10.1.1 Application Curves
    2. 10.2 Application Information
      1. 10.2.1 Typical Application
        1. 10.2.1.1 Design 1: High Voltage – Fast AC Signal Monitoring For Power Fault Detection
          1. 10.2.1.1.1 Design Requirements
          2. 10.2.1.1.2 Detailed Design Procedure
    3. 10.3 Power Supply Recommendations
      1. 10.3.1 Power Dissipation and Device Operation
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
      3. 10.4.3 Creepage Distance
  12. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.5.1 Sense Time Delay Configuration

The time delay (tCTS) can be programmed by connecting a capacitor between CTS1 pin and GND, CTS2 for channel 2. In this section CTSx represent either channel 1 or channel 2.R

The relationship between external capacitor CCTSx_EXT (typ) and the time delay tCTSx (typ) is given by Equation 4.

Equation 4. tCTSx (typ) = -In (0.28) x RCTSx (typ) x CCTSx_EXT (typ) + tCTSx (no cap)

RCTSx = is in kilo ohms (kOhms)

CCTSX_EXT = is given in microfarads (μF)

tCTSx = is the sense time delay (ms)

The sense delay varies according to three variables: the external capacitor (CCTSx_EXT), CTS pin internal resistance (RCTSx) provided in Section 7.5, and a constant. The minimum and maximum variance due to the constant is show in Equation 5 and Equation 6:

Equation 5. tCTSx (min) = -ln (0.31) x RCTSx (min) x CCTSx_EXT (min) + tCTSx (no cap (min))
Equation 6. tCTSx (max) = -ln (0.25) x RCTSx (max) x CCTSx_EXT (max) + tCTSx (no cap (max))

The recommended maximum sense delay capacitor for the TPS37 is limited to 10 μF as this ensures enough time for the capacitor to fully discharge when a voltage fault occurs. Also, having a too large of a capacitor value can cause very slow charge up (rise times) and system noise can cause the the internal circuit to trip earlier or later near the threshold. This leads to variation in time delay where it can make the delay accuracy worse in the presence of system noise.

When a voltage fault occurs, the previously charged up capacitor discharges and if the monitored voltage returns from the fault condition before the delay capacitor discharges completely, the delay will be shorter than expected. The capacitor will begin charging from a voltage above zero and resulting in shorter than expected time delay. A larger delay capacitor can be used so long as the capacitor has enough time between fault events to fully discharge during the duration of the voltage fault. To ensure the capacitor is fully discharged, the time period or time duration between fault events needs to be greater than 10% of the programmed sense time delay.