SBVS240C November   2014  – February 2019 TPS3701

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application
      2.      Typical Error vs Junction Temperature
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Inputs (INA, INB)
      2. 7.3.2 Outputs (OUTA, OUTB)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation (VDD > UVLO)
      2. 7.4.2 Undervoltage Lockout (V(POR) < VDD < UVLO)
      3. 7.4.3 Power-On-Reset (VDD < V(POR))
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Window Voltage Detector Considerations
      2. 8.1.2 Input and Output Configurations
      3. 8.1.3 Immunity to Input Pin Voltage Transients
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2 Detailed Design Procedure

  1. Determine the minimum total resistance of the resistor network necessary to achieve the current consumption specification by using Equation 1. For this example, the current flow through the resistor network was chosen to be 13 µA; a lower current can be selected. However, take care to avoid leakage currents that are artifacts of the manufacturing process. Leakage currents significantly impact the accuracy if they are greater than 1% of the resistor network current.
    2. Equation 5. TPS3701 RTotal_eqn.gif

    where

    • VMON(OV) is the target voltage at which an overvoltage condition is detected as VMON rises.
    • I is the current flowing through the resistor network.
  2. After RTOTAL is determined, R3 can be calculated using Equation 6. Select the nearest 1% resistor value for R3. In this case, 30.9 kΩ is the closest value.
    3. Equation 6. TPS3701 R3_eqn.gif
  3. Use Equation 7 to calculate R2. Select the nearest 1% resistor value for R2. In this case, 6.81 kΩ is the closest value.
    4. Equation 7. TPS3701 R2_eqn.gif
  4. Use Equation 8 to calculate R1. Select the nearest 1% resistor value for R1. In this case, 2 MΩ is the closest value.
    5. Equation 8. TPS3701 R1_eqn.gif
  5. The worst-case tolerance can be calculated by referring to Equation 13 in application report Optimizing Resistor Dividers at a Comparator Input (SLVA450). An example of the rising threshold error, VMON(OV), is given in Equation 9:
    6. Equation 9. TPS3701 tolerance_eqn.gif

    where

    • % TOL(VIT+(INB)) is the tolerance of the INB positive threshold.
    • % ACC is the total tolerance of the VMON(OV) voltage.
    • % TOLR is the tolerance of the resistors selected.
  6. When the outputs switch to the high-Z state, the rise time of the OUTA or OUTB node depends on the pull-up resistance and the capacitance on the node. Choose pull-up resistors that satisfy the downstream timing requirements; 100-kΩ resistors are a good choice for low-capacitive loads.