SBVS240C November   2014  – February 2019 TPS3701

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application
      2.      Typical Error vs Junction Temperature
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Inputs (INA, INB)
      2. 7.3.2 Outputs (OUTA, OUTB)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation (VDD > UVLO)
      2. 7.4.2 Undervoltage Lockout (V(POR) < VDD < UVLO)
      3. 7.4.3 Power-On-Reset (VDD < V(POR))
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Window Voltage Detector Considerations
      2. 8.1.2 Input and Output Configurations
      3. 8.1.3 Immunity to Input Pin Voltage Transients
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.1 Inputs (INA, INB)

The TPS3701 combines two comparators with a precision reference voltage. Each comparator has one external input; the other input is connected to the internal reference. The rising threshold on INB and the falling threshold on INA are designed and trimmed to be equal to the reference voltage (400 mV). This configuration optimizes the device accuracy when used as a window voltage detector. Both comparators also have built-in hysteresis that proves immunity to noise and ensures stable operation.

The INA and INB inputs swings from ground to 1.7 V (7.0 V absolute maximum), regardless of the device supply voltage used. Although not required in most cases, it is good analog design practice to place a 1-nF to 10-nF bypass capacitor at the comparator input for noisy applications in order to reduce sensitivity to transient voltage changes on the monitored signal.

For comparator A, the corresponding output (OUTA) is driven to logic low when the input INA voltage drops below VIT–(INA). When the voltage exceeds VIT+(INA), OUTA goes to a high-impedance state; see Figure 1.

For comparator B, the corresponding output (OUTB) is driven to logic low when the voltage at input INB exceeds VIT+(INB). When the voltage drops below VIT–(INB) OUTB goes to a high-impedance state; see Figure 1. Together, these two comparators form a window voltage detector function as described in the Window Voltage Detector Considerations section.