SNVSBS9C March   2021  – May 2024 TPS3704-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Nomenclature
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 VDD
      2. 7.3.2 SENSEx Input
        1. 7.3.2.1 Immunity to SENSEx Pins Voltage Transients
          1. 7.3.2.1.1 SENSEx Hysteresis
      3. 7.3.3 RESETx/RESETx
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation (VDD > VDD(MIN))
      2. 7.4.2 Undervoltage Lockout (VPOR < VDD < UVLO)
      3. 7.4.3 Power-On Reset (VDD < VPOR)
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Voltage Threshold Accuracy
      2. 8.1.2 Adjustable Voltage Thresholds
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1: Multi-Rail Window Monitoring for Microcontroller Power Rails
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
      2. 8.2.2 Design 2: Manual Self-Test Option for Enhanced Functional Safety Use Cases
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Guidelines
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

TPS3704-Q1 DDF Package8-PIN SOT23TPS37041-Q1 (Top View)Figure 5-1 DDF Package
8-PIN SOT23
TPS37041-Q1 (Top View)
TPS3704-Q1 DDF Package8-PIN SOT23TPS37042-Q1 (Top View)Figure 5-2 DDF Package
8-PIN SOT23
TPS37042-Q1 (Top View)
TPS3704-Q1 DDF Package8-PIN SOT23TPS37043-Q1 (Top View)Figure 5-3 DDF Package
8-PIN SOT23
TPS37043-Q1 (Top View)
TPS3704-Q1 DDF Package8-PIN SOT23TPS37044-Q1 (Top View)Figure 5-4 DDF Package
8-PIN SOT23
TPS37044-Q1 (Top View)
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NAME TPS37041
-Q1		 TPS37042
-Q1		 TPS37043
-Q1		 TPS37044
-Q1
VDD 1 1 1 1 I Supply Input. Bypass with a 0.1µF capacitor to GND.
SENSE1 2 2 2 2 I Connect directly to a monitored voltage. RESET1/RESET1 is asserted when SENSE1 falls outside of the window threshold. No external capacitor is required for this SENSE1 pin. For the TPS37044-Q1 (quad version)
RESET1/RESET1 asserts when either SENSE1 or SENSE2 fall outside of the window threshold. For noisy applications, placing a 10nF to 100nF ceramic capacitor close to this pin may be needed for optimum performance. Leave this pin floating if not used.
SENSE2 — 3 3 3 I Connect directly to a monitored voltage. RESET2/RESET2 is asserted when SENSE2 falls outside of window threshold. No external capacitor is required for the SENSE2 pin. For the TPS37044-Q1 (quad version)
RESET1/RESET1 asserts when either SENSE1 or SENSE2 fall outside of the window threshold. For noisy applications, placing a 10nF to 100nF ceramic capacitor close to this pin may be needed for optimum performance. Leave this pin floating if not used.
SENSE3 — — 5 5 I Connect directly to monitored voltage. RESET3/RESET3 is asserted when SENSE3 falls outside of window threshold. No external capacitor is required for SENSE3 pin. For TPS37044-Q1 (quad version)
RESET2/RESET2 asserts when either SENSE3 or SENSE4 falls outside of window threshold. For noisy applications, placing a 10nF to 100nF ceramic capacitor close to this pin may be needed for optimum performance. If the input pin is not being used, it can be left floating.
SENSE4 — — — 6 I Connect directly to a monitored voltage. For TPS37044-Q1 (quad version) RESET2/RESET2 asserts when either SENSE3 or SENSE4 fall outside of the window threshold. For noisy applications, placing a 10nF to 100nF ceramic capacitor close to this pin may be needed for optimum performance. Leave this pin floating if not used.
RESET1 8 8 8 8 O RESET1/RESET1 asserts when SENSE1 falls outside of the overvoltage or undervoltage threshold window. RESET1/RESET1 stays asserted for the reset timeout period after SENSE1 fall back within the window threshold. Active-low, open-drain reset output, requires an external pullup resistor. For the TPS37044-Q1, RESET1/RESET1 asserts when either SENSE1 or SENSE2 falls outside of the window threshold. Leave this pin floating if not used.
For the TPS37044F-Q1 option, any SENSEx channels that detect an
overvoltage (OV) fault, this pin is asserted.
RESET2 — 7 7 7 O RESET2/RESET2 asserts when SENSE2 falls outside of the overvoltage or undervoltage threshold window. RESET2/RESET2 stays asserted for the reset timeout period after SENSE2 falls back within the window threshold. Active-low, open-drain reset output, requires an external pullup resistor. For the TPS37044-Q1, RESET2/RESET2 asserts when either SENSE3 or SENSE4 fall outside of the window threshold. Leave this pin floating if not used.
For the TPS37044F-Q1 option, any SENSEx channels that detect an
undervoltage (UV) fault, this pin is asserted.
RESET3 — — 6 — O RESET3/RESET3 asserts when SENSE3 falls outside of the overvoltage or undervoltage threshold window. RESET3/RESET3 stays asserted for the reset timeout period after SENSE3 falls back within the window threshold. Active-low, open-drain reset output, requires an external pullup resistor. Leave this pin floating if not being used.
GND 4 4 4 4 — Ground
NC 3,5,6,7 5,6 — — — No connect