SNVSBS9C March   2021  – May 2024 TPS3704-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Nomenclature
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 VDD
      2. 7.3.2 SENSEx Input
        1. 7.3.2.1 Immunity to SENSEx Pins Voltage Transients
          1. 7.3.2.1.1 SENSEx Hysteresis
      3. 7.3.3 RESETx/RESETx
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation (VDD > VDD(MIN))
      2. 7.4.2 Undervoltage Lockout (VPOR < VDD < UVLO)
      3. 7.4.3 Power-On Reset (VDD < VPOR)
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Voltage Threshold Accuracy
      2. 8.1.2 Adjustable Voltage Thresholds
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1: Multi-Rail Window Monitoring for Microcontroller Power Rails
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
      2. 8.2.2 Design 2: Manual Self-Test Option for Enhanced Functional Safety Use Cases
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Guidelines
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Timing Requirements

At 1.7V ≤ VDD ≤ 6.0V,  RESETx voltage (VRESETx) = 10kΩ to VDD, RESETx load = 10pF, and over the operating free-air temperature range of – 40°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C, typical conditions at VDD = 3.3V.
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
tD Reset release time delay Fixed delay option tD < 4ms, overdrive = 10% -40 tD 40 %
tD Reset release time delay Fixed delay option tD > 5ms, overdrive = 10% -30 tD 30 %
tPD Propagation detect delay (1) Fixed time delay tD > 1ms, overdrive 10% 10 µs
tGI(VIT-) Glitch Immunity Undervoltage (5% overdrive) (2)  2 µs
tGI(VIT+) Glitch Immunity Overvoltage (5% overdrive) (2)  2 µs
tR Ouptut rise (Push-Pull) (2) (3) 25 ns
tR Output rise time (Open-Drain) (2) (3) 2.2 µs
tF Output fall time (2) (3) 0.2 µs
tSTRT Startup delay (4) 1 ms
(1) tPD measured from threshold trip point (VIT-(UV) or VIT+(OV)) to RESETx VOL voltage
(2) 5% Overdrive from threshold. Overdrive % = [(VSENSEx - VIT) / VIT]; Where VIT stands for VIT-(UV) or VIT+(OV)
(3) Output transitions from VOL to VOH or  (VRESETx) for rise times and VOH  or (VRESETx) to VOL for fall times.
(4) During the power-on sequence, VDD must be at or above VDD(MIN) for at least tSTRT + tD before the output is in the correct state. when VDD is between VDD(MIN) and VPOR the RESETx pin will be engaged