SNVSBZ2E March   2021  – December 2023 TPS3704

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Nomenclature
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD
      2. 7.3.2 SENSEx Input
        1. 7.3.2.1 Immunity to SENSEx Pins Voltage Transients
          1. 7.3.2.1.1 SENSEx Hysteresis
      3. 7.3.3 RESETx/RESETx
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation (VDD > VDD(MIN))
      2. 7.4.2 Undervoltage Lockout (VPOR < VDD < UVLO)
      3. 7.4.3 Power-On Reset (VDD < VPOR)
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Voltage Threshold Accuracy
      2. 8.1.2 Adjustable Voltage Thresholds
    2. 8.2 Typical Application
      1. 8.2.1 Design 1: Multi-Rail Window Monitoring for Microcontroller Power Rails
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
      2. 8.2.2 Design 2: Manual Self-Test Option for Enhanced Functional Safety Use Cases
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Guidelines
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.8 Typical Characteristics

Typical characteristics show the typical performance of the TPS3704x device. Test conditions are TA = 25°C, VDD = 3.3 V, and Rpull-upx = 10 kΩ, CLOAD = 50 pF, unless otherwise noted.

GUID-20210214-CA0I-LTN7-N0PR-DGDGJ2V00KGQ-low.gifFigure 6-3 Undervoltage Accuracy vs Temperature
GUID-20210214-CA0I-TXS1-9B3W-75CQGFJCRTX2-low.gifFigure 6-5 Undervoltage Hysteresis Voltage Accuracy vs Temperature
GUID-20210214-CA0I-TTQP-NL5D-B6813PC5HPL5-low.gif
Output ( RESETx Pin) = High
Figure 6-7 Supply Current vs Temperature
GUID-20210214-CA0I-W67M-T0JH-RHRPHPF6W7JK-low.gif
VDD = 5 V
Figure 6-9 Low-Level CH 1 Output Voltage vs RESET1 Current
GUID-20210214-CA0I-54Z6-L9SS-WHB86KLCBXN4-low.gif
VDD = 5 V
Figure 6-11 Low-Level CH 2 Output Voltage vs RESET2 Current
GUID-20210214-CA0I-CHGF-JBMT-SFRRKKSPP3GM-low.gif
VDD = 5 V
Figure 6-13 Low-Level CH 3 Output Voltage vs RESET3 Current
GUID-20210214-CA0I-PTR7-4JMH-0PGR8FRXWKPS-low.gif
VDD = 5 V
Figure 6-15 Low-Level CH 4 Output Voltage vs RESET4 Current
GUID-20210218-CA0I-BNPS-CTF1-02SW5JPV6JK4-low.svg
VDD = 1.7 V
Figure 6-17 SENSE1 Glitch Immunity (VIT+) vs Overdrive
GUID-20210218-CA0I-CR38-V9WX-6LKM6R8LLZ2R-low.svg
VDD = 3.3 V
Figure 6-19 SENSE1 Glitch Immunity (VIT+) vs Overdrive
GUID-20210218-CA0I-MDDT-NLNK-KWKHXJ1ZJMHH-low.svg
VDD = 5 V
Figure 6-21 SENSE1 Glitch Immunity (VIT+) vs Overdrive
GUID-20210214-CA0I-C1J9-MJMV-2V0HNMWFRM4Z-low.gifFigure 6-4 Overvoltage Accuracy vs Temperature
GUID-20210214-CA0I-LQQP-Z2LP-45H5N2HLQMJM-low.gifFigure 6-6 Overvoltage Hysteresis Voltage Accuracy vs Temperature
GUID-20210214-CA0I-G1JK-K7M8-TBMNGHJBQRQ5-low.gif
VDD = 1.7 V
Figure 6-8 Low-Level CH 1 Output Voltage vs RESET1 Current
GUID-20210214-CA0I-4BZW-P51D-0BWW8K68FMWT-low.gif
VDD = 1.7 V
Figure 6-10 Low-Level CH 2 Output Voltage vs RESET2 Current
GUID-20210214-CA0I-SZKT-VRVQ-J62SSDJ45NXL-low.gif
VDD = 1.7 V
Figure 6-12 Low-Level CH 3 Output Voltage vs RESET3 Current
GUID-20210214-CA0I-6F8W-9MKZ-2K7L5WJRNPVW-low.gif
VDD = 1.7 V
Figure 6-14 Low-Level CH 4 Output Voltage vs RESET4 Current
GUID-20210218-CA0I-PCRH-W8PP-TVSV00RTPWF6-low.svg
VDD = 1.7 V
Figure 6-16 SENSE1 Glitch Immunity (VIT-) vs Overdrive
GUID-20210218-CA0I-4F60-R30J-BK6PCL7M4LZD-low.svg
VDD = 3.3 V
Figure 6-18 SENSE1 Glitch Immunity (VIT-) vs Overdrive
GUID-20210218-CA0I-FFFP-TCV0-D83ZDSKKFTCK-low.svg
VDD = 5 V
Figure 6-20 SENSE1 Glitch Immunity (VIT-) vs Overdrive