SNVSBZ2E March 2021 – December 2023 TPS3704
PRODUCTION DATA
PARAMETER | DESIGN REQUIREMENT | DESIGN RESULT |
---|---|---|
Monitored rails | 3.3-VI/O nominal, with alerts if outside of ±8% of 3.3 V (including device accuracy), 10 ms reset delay | Worst case VIT+(OV) = 3.533 V (7.06%)
Worst case VIT–(UV) = 3.071 V (-6.94%) |
1.2-VCORE nominal, with alerts if outside of ±5% of 1.2 V (including device accuracy), 10 ms reset delay | Worst case VIT+(OV) = 1.2484 V (4.03%)
Worst case VIT–(UV) = 1.1524 V (-3.97%) | |
Output logic voltage | 5-V CMOS | 5-V CMOS |
Maximum system supervision current consumption | 25 µA | 5.5 µA (15 µA max) |