SNVSBZ2E March   2021  – December 2023 TPS3704

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Nomenclature
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD
      2. 7.3.2 SENSEx Input
        1. 7.3.2.1 Immunity to SENSEx Pins Voltage Transients
          1. 7.3.2.1.1 SENSEx Hysteresis
      3. 7.3.3 RESETx/RESETx
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation (VDD > VDD(MIN))
      2. 7.4.2 Undervoltage Lockout (VPOR < VDD < UVLO)
      3. 7.4.3 Power-On Reset (VDD < VPOR)
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Voltage Threshold Accuracy
      2. 8.1.2 Adjustable Voltage Thresholds
    2. 8.2 Typical Application
      1. 8.2.1 Design 1: Multi-Rail Window Monitoring for Microcontroller Power Rails
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
      2. 8.2.2 Design 2: Manual Self-Test Option for Enhanced Functional Safety Use Cases
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Guidelines
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.1 Design Requirements

Table 8-2 Design Requirements
PARAMETER DESIGN REQUIREMENT DESIGN RESULT
Monitored rails 3.3-V AVDD nominal, with alerts if outside of ±4% of 3.3 V (including device accuracy), 10-ms reset delay Worst case VIT+(OV) = 3.432 V (+4%)
Worst case VIT–(UV) = 3.168 V (–4%)
1.8-V IOVDD nominal, with alerts if outside of ±4% of 1.8 V (including device accuracy), 10-ms reset delay Worst case VIT+(OV) = 1.872 V (+4%)
Worst case VIT–(UV) = 1.728 V (–4%)
1.2-V DVDD nominal, with alerts if outside of ±4% of 1.2 V (including device accuracy), 10-ms reset delay Worst case VIT+(OV) = 1.248 V (+4%)
Worst case VIT–(UV) = 1.152 V (–4%)
SENSE4
(Self-test Option)		 100-kΩ pullup resistor to VDD with NFET pulldown transistor to GND UV_Trig = High - causing SENSE4 pin going low
UV_Trig = Low - in normal operation
Output logic voltage 5-V CMOS 5-V CMOS
Max system
IDD current		 25 µA 5.5 µA (20 µA maximum)