SBVS420A March   2022  – September 2023 TPS3760

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (VDD)
        1. 8.3.1.1 Undervoltage Lockout (VPOR < VDD < UVLO)
        2. 8.3.1.2 Power-On Reset (VDD < VPOR )
      2. 8.3.2 SENSE
        1. 8.3.2.1 SENSE Hysteresis
      3. 8.3.3 Output Logic Configurations
        1. 8.3.3.1 Open-Drain
        2. 8.3.3.2 Push-Pull
        3. 8.3.3.3 Active-High (RESET)
        4. 8.3.3.4 Active-Low (RESET)
      4. 8.3.4 User-Programmable Reset Time Delay
        1. 8.3.4.1 Reset Time Delay Configuration
      5. 8.3.5 User-Programmable Sense Delay
        1. 8.3.5.1 Sense Time Delay Configuration
      6. 8.3.6 Manual RESET (CTR / MR) Input
      7. 8.3.7 RESET Latch Mode
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Adjustable Voltage Thresholds
    3. 9.3 Typical Application
      1. 9.3.1 Design 1: Off-Battery Monitoring
        1. 9.3.1.1 Design Requirements
        2. 9.3.1.2 Detailed Design Procedure
        3. 9.3.1.3 Application Curves
  11. 10Power Supply Recommendations
    1. 10.1 Power Dissipation and Device Operation
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Creepage Distance
  13. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.4.1 Reset Time Delay Configuration

The time delay (tCTR) can be programmed by connecting a capacitor between CTR pin and GND.

The relationship between external capacitor CCTR_EXT (typ) and the time delay tCTR (typ) is given by Equation 1.

Equation 1. tCTR (typ) = -ln (0.28) x RCTR (typ) x CCTR_EXT (typ) + tCTR (no cap)

RCTR (typ) = is in kilo ohms (kOhms)

CCTR_EXT (typ) = is given in microfarads (μF)

tCTR (typ) = is the reset time delay (ms)

The reset delay varies according to three variables: the external capacitor (CCTR_EXT), CTR pin internal resistance (RCTR) provided in Section 7, and a constant. The minimum and maximum variance due to the constant is show in Equation 5 and Equation 6:

Equation 2. tCTR (min) = -ln (0.31) x RCTR (min) x CCTR_EXT (min) + tCTR (no cap (min))
Equation 3. tCTR (max) = -ln (0.25) x RCTR (max) x CCTR_EXT (max) + tCTR (no cap (max))

The recommended maximum reset delay capacitor for the TPS3760 is limited to 10 μF as this ensures enough time for the capacitor to fully discharge when a voltage fault occurs. Also, having a too large of a capacitor value can cause very slow charge up (rise times) due to capacitor leakage and system noise can cause the the internal circuit to trip earlier or later near the threshold. This leads to variation in time delay where it can make the delay accuracy worse in the presence of system noise.

When a voltage fault occurs, the previously charged up capacitor discharges and if the monitored voltage returns from the fault condition before the delay capacitor discharges completely, the delay will be shorter than expected. The capacitor will begin charging from a voltage above zero and resulting in shorter than expected time delay. A larger delay capacitor can be used so long as the capacitor has enough time to fully discharge during the duration of the voltage fault. To ensure the capacitor is fully discharged, the time period or duration of the voltage fault needs to be greater than 5% of the programmed reset time delay.