SNVSCE6A
October 2023 – May 2024
TPS3762-Q1
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Device Nomenclature
5
Device Comparison
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Switching Requirements
7.7
Timing Requirements
8
Timing Diagrams
9
Typical Characteristics
10
Detailed Description
10.1
Overview
10.2
Functional Block Diagram
10.3
Feature Description
10.3.1
Input Voltage (VDD)
10.3.1.1
Undervoltage Lockout (VPOR < VDD < UVLO)
10.3.1.2
Power-On Reset (VDD < VPOR )
10.3.2
SENSE
10.3.2.1
Reverse Polarity Protection
10.3.2.2
SENSE Hysteresis
10.3.3
Output Logic Configurations
10.3.3.1
Open-Drain
10.3.3.2
Active-Low (RESET)
10.3.3.3
Latching
10.3.3.4
UVBypass
10.3.4
User-Programmable Reset Time Delay
10.3.4.1
Reset Time Delay Configuration
10.3.5
User-Programmable Sense Delay
10.3.5.1
Sense Time Delay Configuration
10.3.6
Built-In Self-Test
10.4
Device Functional Modes
11
Application and Implementation
11.1
Application Information
11.2
Adjustable Voltage Thresholds
11.3
Typical Application
11.3.1
Design 1: Off-Battery Monitoring
11.3.1.1
Design Requirements
11.3.1.2
Detailed Design Procedure
11.3.1.2.1
Setting Voltage Threshold
11.3.1.2.2
Meeting the Sense and Reset Delay
11.3.1.2.3
Setting Supply Voltage
11.3.1.2.4
Initiating Built-In Self-Test and Clearing Latch
11.3.1.3
Application Curves
11.4
Power Supply Recommendations
11.4.1
Power Dissipation and Device Operation
11.5
Layout
11.5.1
Layout Guidelines
11.5.2
Layout Example
12
Device and Documentation Support
12.1
Receiving Notification of Documentation Updates
12.2
Support Resources
12.3
Trademarks
12.4
Electrostatic Discharge Caution
12.5
Glossary
13
Revision History
14
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DDF|8
MPDS569D
Thermal pad, mechanical data (Package|Pins)
Orderable Information
snvsce6a_oa
snvsce6a_pm
10.3
Feature Description