SNVSCE6A October   2023  – May 2024 TPS3762-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Nomenclature
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Requirements
    7. 7.7 Timing Requirements
  9. 8 Timing Diagrams
  10. 9 Typical Characteristics
  11. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Input Voltage (VDD)
        1. 10.3.1.1 Undervoltage Lockout (VPOR < VDD < UVLO)
        2. 10.3.1.2 Power-On Reset (VDD < VPOR )
      2. 10.3.2 SENSE
        1. 10.3.2.1 Reverse Polarity Protection
        2. 10.3.2.2 SENSE Hysteresis
      3. 10.3.3 Output Logic Configurations
        1. 10.3.3.1 Open-Drain
        2. 10.3.3.2 Active-Low (RESET)
        3. 10.3.3.3 Latching
        4. 10.3.3.4 UVBypass
      4. 10.3.4 User-Programmable Reset Time Delay
        1. 10.3.4.1 Reset Time Delay Configuration
      5. 10.3.5 User-Programmable Sense Delay
        1. 10.3.5.1 Sense Time Delay Configuration
      6. 10.3.6 Built-In Self-Test
    4. 10.4 Device Functional Modes
  12. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Adjustable Voltage Thresholds
    3. 11.3 Typical Application
      1. 11.3.1 Design 1: Off-Battery Monitoring
        1. 11.3.1.1 Design Requirements
        2. 11.3.1.2 Detailed Design Procedure
          1. 11.3.1.2.1 Setting Voltage Threshold
          2. 11.3.1.2.2 Meeting the Sense and Reset Delay
          3. 11.3.1.2.3 Setting Supply Voltage
          4. 11.3.1.2.4 Initiating Built-In Self-Test and Clearing Latch
        3. 11.3.1.3 Application Curves
    4. 11.4 Power Supply Recommendations
      1. 11.4.1 Power Dissipation and Device Operation
    5. 11.5 Layout
      1. 11.5.1 Layout Guidelines
      2. 11.5.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

TPS3762-Q1 DDF Package,8-Pin SOT-23,TPS3762-Q1 (Top View)Figure 6-1 DDF Package,
8-Pin SOT-23,
TPS3762-Q1 (Top View)
Table 6-1 Pin Functions

PIN

I/ODESCRIPTION
NAMENO.
VDD1IInput Supply Voltage: Supply voltage pin. For noisy systems, bypass with a 0.1µF capacitor to GND.
SENSE2I

Sense Voltage: Connect this pin to the supply rail that must be monitored. See Section 8.3.2 for more details.

Sensing Topology: Overvoltage (OV) or Undervoltage (UV) or Window (OV + UV)

GND

3

-Ground. Ground pin. All GND pins must be electrically connected to the board ground.
RESET4O

Output Reset Signal: RESET asserts when SENSE crosses the voltage threshold after the sense time delay, set by CTS, and remains asserted for the reset time delay period, set by CTR, after SENSE transitions out of a fault condition. For latch variants RESET remains asserted until the latch is cleared. The active low open-drain reset output requires an external pullup resistor. See Section 8.3.3.2 for more details.

Output topology: Open-Drain Active-Low

BIST5

O

Built-In Self-Test: BIST asserts when a logic high input occurs on the BIST_EN / LATCH_CLR or BIST_EN pin, this initiates the internal BIST testing. BIST recovers after tBIST to signify BIST completed successfully. BIST remains asserted for a time period longer than tBIST if there is a failure during BIST. BIST active-low open-drain output requires an external pullup resistor. See Section 8.3.6 for more details.

BIST_EN / LATCH_CLR

6

I

Built-in Self-test Enable and Latch Clear: A logic high input must occur on the BIST_EN / LATCH_CLR to initate BIST and clear a latched OV/UV fault. See Section 8.3.6 for more details.
CTR7

O

RESET Time Delay: User-programmable reset time delay for RESET. Connect an external capacitor for adjustable time delay or leave the pin floating for the shortest delay. See Section8.3.4 for more details.

CTS

8

O

SENSE Time Delay: User-programmable sense time delay for SENSE. Connect an external capacitor for adjustable time delay or leave the pin floating for the shortest delay. See Section 8.3.5 for more details.