SNVSCE6A October   2023  – May 2024 TPS3762-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Nomenclature
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Requirements
    7. 7.7 Timing Requirements
  9. 8 Timing Diagrams
  10. 9 Typical Characteristics
  11. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Input Voltage (VDD)
        1. 10.3.1.1 Undervoltage Lockout (VPOR < VDD < UVLO)
        2. 10.3.1.2 Power-On Reset (VDD < VPOR )
      2. 10.3.2 SENSE
        1. 10.3.2.1 Reverse Polarity Protection
        2. 10.3.2.2 SENSE Hysteresis
      3. 10.3.3 Output Logic Configurations
        1. 10.3.3.1 Open-Drain
        2. 10.3.3.2 Active-Low (RESET)
        3. 10.3.3.3 Latching
        4. 10.3.3.4 UVBypass
      4. 10.3.4 User-Programmable Reset Time Delay
        1. 10.3.4.1 Reset Time Delay Configuration
      5. 10.3.5 User-Programmable Sense Delay
        1. 10.3.5.1 Sense Time Delay Configuration
      6. 10.3.6 Built-In Self-Test
    4. 10.4 Device Functional Modes
  12. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Adjustable Voltage Thresholds
    3. 11.3 Typical Application
      1. 11.3.1 Design 1: Off-Battery Monitoring
        1. 11.3.1.1 Design Requirements
        2. 11.3.1.2 Detailed Design Procedure
          1. 11.3.1.2.1 Setting Voltage Threshold
          2. 11.3.1.2.2 Meeting the Sense and Reset Delay
          3. 11.3.1.2.3 Setting Supply Voltage
          4. 11.3.1.2.4 Initiating Built-In Self-Test and Clearing Latch
        3. 11.3.1.3 Application Curves
    4. 11.4 Power Supply Recommendations
      1. 11.4.1 Power Dissipation and Device Operation
    5. 11.5 Layout
      1. 11.5.1 Layout Guidelines
      2. 11.5.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11.2 Adjustable Voltage Thresholds

Figure 11-1 illustrates an example of how to adjust the voltage threshold with external resistor dividers. The resistors can be calculated depending on the desired voltage threshold and device part number. TI recommends using the adjustable (0.8V voltage threshold device) when setting adjustable voltage thresholds. This variant bypasses the internal resistor ladder.

For example, consider a 12V rail, VMON, being monitored for overvoltage (OV) using of the TPS3762D02OVDDFRQ1 variant, as shown in Figure 11-1. The monitored OV threshold, denoted as VMON+, is the desired voltage where the device asserts the reset. For this example VMON+ = 35V. To assert an overvoltage reset the voltage at the sense pin, VSENSE, needs to be equal to the input threshold positive, VITP. For this example variant VSENSE = VITP = 0.8V. Using R1 and R2 the correlation between VMON+ and VSENSE can be seen in Equation 8. Assuming R2 = 10kΩ, and R1 can be calculated as R1 = 427.5kΩ.

Equation 7. VSENSE = VMON+ × (R2 ÷ (R1 + R2))

The TPS3762D02OVDDFRQ1 comes with variant specific 2%, 5%, or 10% voltage threshold hysteresis. For the reset signal to become deasserted, VMON must go below VITP - VHYS. For this example variant a 2% voltage threshold hysteresis was selected. Therefore, VMON equals 34.3V when the reset signal becomes deasserted.

There are inaccuracies that must be taken into consideration while adjusting voltage thresholds. Aside from the tolerance of the resistor divider, there is the internal resistance of the SENSE pin that can affect the accuracy of the resistor divider. Although expected to be very high impedance, users are recommended to calculate the values for the design specifications. The internal SENSE resistance (RSENSE) can be calculated by the SENSE voltage (VSENSE) divided by the SENSE current (ISENSE) as shown in Equation 9. VSENSE can be calculated using Equation 7 depending on the resistor divider and monitored voltage. ISENSE can be calculated using Equation 8.

Equation 8. ISENSE = [(VMON - VSENSE) ÷ R1] - (VSENSE ÷ R2)
Equation 9. RSENSE = VSENSE ÷ ISENSE
TPS3762-Q1 Adjustable Voltage Threshold with External Resistor DividersFigure 11-1 Adjustable Voltage Threshold with External Resistor Dividers