SNVSCE6A October   2023  – May 2024 TPS3762-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Nomenclature
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Requirements
    7. 7.7 Timing Requirements
  9. 8 Timing Diagrams
  10. 9 Typical Characteristics
  11. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Input Voltage (VDD)
        1. 10.3.1.1 Undervoltage Lockout (VPOR < VDD < UVLO)
        2. 10.3.1.2 Power-On Reset (VDD < VPOR )
      2. 10.3.2 SENSE
        1. 10.3.2.1 Reverse Polarity Protection
        2. 10.3.2.2 SENSE Hysteresis
      3. 10.3.3 Output Logic Configurations
        1. 10.3.3.1 Open-Drain
        2. 10.3.3.2 Active-Low (RESET)
        3. 10.3.3.3 Latching
        4. 10.3.3.4 UVBypass
      4. 10.3.4 User-Programmable Reset Time Delay
        1. 10.3.4.1 Reset Time Delay Configuration
      5. 10.3.5 User-Programmable Sense Delay
        1. 10.3.5.1 Sense Time Delay Configuration
      6. 10.3.6 Built-In Self-Test
    4. 10.4 Device Functional Modes
  12. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Adjustable Voltage Thresholds
    3. 11.3 Typical Application
      1. 11.3.1 Design 1: Off-Battery Monitoring
        1. 11.3.1.1 Design Requirements
        2. 11.3.1.2 Detailed Design Procedure
          1. 11.3.1.2.1 Setting Voltage Threshold
          2. 11.3.1.2.2 Meeting the Sense and Reset Delay
          3. 11.3.1.2.3 Setting Supply Voltage
          4. 11.3.1.2.4 Initiating Built-In Self-Test and Clearing Latch
        3. 11.3.1.3 Application Curves
    4. 11.4 Power Supply Recommendations
      1. 11.4.1 Power Dissipation and Device Operation
    5. 11.5 Layout
      1. 11.5.1 Layout Guidelines
      2. 11.5.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

At VDD(MIN) ≤ VDD ≤ VDD(MAX), CTR = CTS = open, output RESET pull-up resistor RPU = 10kΩ, voltage VPU = 5.5V, output BIST pull-up resistor RPU_BIST = 10kΩ, voltage VPU_BIST = 5.5V, and load CLOAD = 10pF. The operating free-air temperature range TA = – 40°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C and VDD = 12V and VIT = 6.5V (VIT refers to VITN or VITP).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
VDD Supply Voltage 2.7 65 V
UVLO (1) Undervoltage Lockout VDD rising above VDD (MIN) 2.6 V
UVLO(HYS) (1) Undervoltage Lockout Hysteresis VDD falling below VDD (MIN) 500 mV
VPOR(RESET) Power on Reset Voltage (2)
RESET, Active Low
(Open-Drain)		 VOL(MAX) = 300mV
IOUT (Sink) = 15µA
 1.4 V
VPOR(BIST) Power on Reset Voltage (2)
BIST, Active Low
(Open-Drain)		 VOL(MAX) = 300mV
IOUT (Sink) = 15µA
 1.4 V
IDD Supply current into VDD pin VIT = 800mV
VDD (MIN) ≤ VDD ≤ VDD (MAX)
 4 8.1 µA
SENSE (Input)
ISENSE Input current
VIT = 800mV
 200 nA
VITN  Input Threshold Negative
(Undervoltage)		 VIT = 800mV (3) -0.9 0.9 %
VITP
Input Threshold Positive 
(Overvoltage)
 		 VIT = 800mV (3) -0.9 0.9 %
VHYS Hysteresis Accuracy (4) VIT = 0.8V
VHYS Range = 2%		 1.5 2 2.5 %
RESET (Output)
Ilkg(OD) Open-Drain leakage VRESET = 5.5V
VITN < VSENSE < VITP		 300 nA
Ilkg(OD) Open-Drain leakage VRESET = 65V
VITN < VSENSE < VITP		 300 nA
VOL (5) Low level output voltage 2.7V ≤ VDD ≤ 65V
IRESET = 2.7mA
 350 mV
Capacitor Timing (CTS, CTR)
RCTR Internal resistance (CTR) 2.96 3.7 4.44 MΩ
RCTS Internal resistance (CTS) 2.96 3.7 4.44 MΩ
Built-in Self-test
Ilkg(BIST) Open-Drain leakage VBIST = 5.5V
VITN < VSENSE < VITP		 300 nA
Ilkg(BIST) Open-Drain leakage VBIST = 3.3V
VITN < VSENSE < VITP		 300 nA
VBIST_OL Low level output voltage 2.7V ≤ VDD ≤ 65V
IBIST = 5mA
 300 mV
VBIST_EN BIST_EN pin logic low input 500 mV
VBIST_EN BIST_EN pin logic high input 1300 mV
VBIST_EN/LATCH_CLR LATCH_CLR pin logic low input 500 mV
VBIST_EN/LATCH_CLR LATCH_CLR pin logic high input 1300 mV
(1) When VDD voltage falls below UVLO, RESET is asserted. VDD slew rate ≤ 100mV / µs
(2) VPOR is the minimum VDD voltage for a controlled output state. Below VPOR, the output cannot be determined. VDD slew rate ≤ 100mV/µs
(3) For adjustable voltage guidelines and resistor selection refer to Adjustable Voltage Thresholds in Application and Implementation section
(4) Hysteresis is with respect to VITP and VITN voltage threshold. VITP has negative hysteresis and VITN has positive hysteresis.
(5) For VOH and VOL relation to output variants refer to Timing Figures after the Timing Requirement Table