SNVSCE6A October   2023  – May 2024 TPS3762-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Nomenclature
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Requirements
    7. 7.7 Timing Requirements
  9. 8 Timing Diagrams
  10. 9 Typical Characteristics
  11. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Input Voltage (VDD)
        1. 10.3.1.1 Undervoltage Lockout (VPOR < VDD < UVLO)
        2. 10.3.1.2 Power-On Reset (VDD < VPOR )
      2. 10.3.2 SENSE
        1. 10.3.2.1 Reverse Polarity Protection
        2. 10.3.2.2 SENSE Hysteresis
      3. 10.3.3 Output Logic Configurations
        1. 10.3.3.1 Open-Drain
        2. 10.3.3.2 Active-Low (RESET)
        3. 10.3.3.3 Latching
        4. 10.3.3.4 UVBypass
      4. 10.3.4 User-Programmable Reset Time Delay
        1. 10.3.4.1 Reset Time Delay Configuration
      5. 10.3.5 User-Programmable Sense Delay
        1. 10.3.5.1 Sense Time Delay Configuration
      6. 10.3.6 Built-In Self-Test
    4. 10.4 Device Functional Modes
  12. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Adjustable Voltage Thresholds
    3. 11.3 Typical Application
      1. 11.3.1 Design 1: Off-Battery Monitoring
        1. 11.3.1.1 Design Requirements
        2. 11.3.1.2 Detailed Design Procedure
          1. 11.3.1.2.1 Setting Voltage Threshold
          2. 11.3.1.2.2 Meeting the Sense and Reset Delay
          3. 11.3.1.2.3 Setting Supply Voltage
          4. 11.3.1.2.4 Initiating Built-In Self-Test and Clearing Latch
        3. 11.3.1.3 Application Curves
    4. 11.4 Power Supply Recommendations
      1. 11.4.1 Power Dissipation and Device Operation
    5. 11.5 Layout
      1. 11.5.1 Layout Guidelines
      2. 11.5.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Switching Requirements

At VDD(MIN) ≤ VDD ≤ VDD(MAX), CTR = CTS = open and enabled, output RESET pull-up resistor RPU = 10kΩ, voltage VPU = 5.5V, output BIST pull-up resistor RPU_BIST = 10kΩ, voltage VPU_BIST = 5.5V, and load CLOAD = 10pF. The operating free-air temperature range TA = – 40°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C and VDD = 12V and VIT = 6.5V (VIT refers to VITN or VITP).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Common Switching Requirements
tCTR(No Cap) RESET release time delay
(CTR)(1)		 VIT = 800mV
CCTR = Open
20% Overdrive from Hysteresis		 350 600 µs
tCTS(No Cap) Sense detect time delay 
(CTS)(2)		 VIT = 800mV
CCTS = Open
20% Overdrive from VIT		 85 100 µs
tSD Startup Delay (3) CCTR = Open 1 ms
BIST Switching Requirements
tBIST_en_pd Rising edge of BIST_EN to BIST asserting 2.3 µs
tBIST_en_pd Rising edge of BIST_EN to RESET asserting 2.3 µs
tBIST_recover Rising edge of BIST to SENSE input valid CCTR = Open, BIST = Enabled 350 600 µs
tBIST BIST run time 3.5 ms
tSD+BIST Startup time with BIST run time 4.5 ms
LATCH Switching Requirements
tBIST_EN/LATCH_CLR_Recover Rising edge of BIST to SENSE input valid CCTR = Open, BIST = Disabled 10 µs
(1) CTR Reset detect time delay:
Overvoltage active-low output is measure from VITP - HYS  to VOH
Undervoltage active-low output is measure from VITN + HYS  to VOH
(2) CTS Sense detect time delay:
Overvoltage active-low output is measure from VITP to VOL
Undervoltage active-low output is measure from VITN to VOL
(3) During the power-on sequence, VDD must be at or above VDD (MIN) for at least tSD+BIST + tCTR before the output is in the correct state based on VSENSE. 
tSD time includes the propagation delay (CCTR = Open). Capacitor on CTR will add time to tSD.