SNVSCM8A October   2023  – December 2023 TPS3762

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Specifications
    2. 6.2 Absolute Maximum Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Requirements
    7. 6.7 Timing Requirements
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristic
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Voltage (VDD)
        1. 7.3.1.1 Undervoltage Lockout (VPOR < VDD < UVLO)
        2. 7.3.1.2 Power-On Reset (VDD < VPOR )
      2. 7.3.2 SENSE
        1. 7.3.2.1 Reverse Polarity Protection
        2. 7.3.2.2 SENSE Hysteresis
      3. 7.3.3 Output Logic Configurations
        1. 7.3.3.1 Open-Drain
        2. 7.3.3.2 Active-Low (RESET)
        3. 7.3.3.3 Latching
      4. 7.3.4 User-Programmable Reset Time Delay
        1. 7.3.4.1 Reset Time Delay Configuration
      5. 7.3.5 User-Programmable Sense Delay
        1. 7.3.5.1 Sense Time Delay Configuration
      6. 7.3.6 Built-In Self-Test
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Adjustable Voltage Thresholds
    3. 8.3 Typical Application
      1. 8.3.1 Design 1: SELV Power Supply Monitoring
        1. 8.3.1.1 Design Requirements
        2. 8.3.1.2 Detailed Design Procedure
          1. 8.3.1.2.1 Setting Voltage Threshold
          2. 8.3.1.2.2 Meeting the Sense and Reset Delay
          3. 8.3.1.2.3 Setting Supply Voltage
          4. 8.3.1.2.4 Initiating Built-In Self-Test and Clearing Latch
        3. 8.3.1.3 Application Curves
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Power Dissipation and Device Operation
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.6 Built-In Self-Test

The TPS3762 has a Built-In Self-Test (BIST) feature that runs diagnostics internally in the device. During power-up BIST is initiated automatically after crossing VDD(min). During BIST the BIST pin and RESET output asserts low and deasserts if the BIST test completes successfully indicating no internal faults in the device. The length of the BIST and BIST assertion is specified by tBIST. If BIST is not successful, the BIST pin will say asserted low signifying an internal fault. The RESET output will stay assert on BIST failure. During BIST, the device is not monitoring the SENSE pin for faults and the RESET is not dependent on the SENSE pin voltage. The BIST sequence of internal tests verifies the internal signal chain of the device by checking for faults on the internal comparators on the SENSE pin, bandgap voltage, and the RESET output. See Figure 7-7 for more details.

GUID-20231211-SS0I-MJVX-PZJZ-XQZR4VVCC3XS-low.svgFigure 7-7 TPS3762 Start-Up Sequence

After a successful power-up sequence, BIST can be initiated any time with a logic high input (VBIST_EN or VBIST_EN/LATCH_CLR > 1.3 V) on the BIST_EN / LATCH_CLR pin. BIST initiates and the BIST pin asserts only if the SENSE pin is not in a overvoltage or undervoltage fault mode. During this BIST test time period, tBIST, BIST pin asserts low to signify that BIST has started and RESET assertion is dependent on the device variant. Upon a successful BIST the BIST pin and RESET pin are deasserted. If BIST is not successful due to the internal device not working properly, the RESET pin and BIST pin remain asserted low signifying a fault internal to the device. See Figure 7-8 and for Figure 7-9 more details.

GUID-20231212-SS0I-T1PZ-MN6W-ZVXDC1MF65MS-low.svgFigure 7-8 BIST With RESET Assertion
GUID-20231206-SS0I-5GR6-HKZR-VGWFJ5TNRP1S-low.svgFigure 7-9 BIST With No RESET Assertion
GUID-20231206-SS0I-ZSW3-T7P2-6Q0H2R6QWXSG-low.svgFigure 7-10 BIST Fail With RESET Assertion
GUID-20231206-SS0I-MVBK-LHK7-XC8QRJWFTHVR-low.svgFigure 7-11 BIST Fail With No RESET Assertion